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Circuit layout generation method and device, computer equipment and storage medium

A technology for circuit layout and integrated circuits, applied in computer-aided design, computing, electrical digital data processing, etc., can solve problems such as low efficiency and achieve the effect of improving efficiency

Pending Publication Date: 2021-11-23
上海阡视科技有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The current method of converting behavior-level description or RTL-level description into gate-level netlist has low efficiency

Method used

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  • Circuit layout generation method and device, computer equipment and storage medium
  • Circuit layout generation method and device, computer equipment and storage medium
  • Circuit layout generation method and device, computer equipment and storage medium

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Embodiment Construction

[0052] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only It is a part of the embodiments of the present disclosure, but not all of them. The components of the disclosed embodiments generally described and illustrated in the figures herein may be arranged and designed in a variety of different configurations. Accordingly, the following detailed description of the embodiments of the present disclosure provided in the accompanying drawings is not intended to limit the scope of the claimed disclosure, but merely represents selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those ski...

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Abstract

The invention provides a circuit layout generation method and device, computer equipment and a storage medium. The circuit layout generation method comprises the following steps: obtaining description information corresponding to multiple levels of function blocks of an integrated circuit; carrying out the following synthesis process on each level of function block according to the sequence of the levels from low to high: for a non-last level of function block in each level of function block, synthesizing the level of function block according to the net list information of a lower level of function block corresponding to the level of function block and the description information of the level of function block, and obtaining a gate-level net list which corresponds to the level function block and meets a preset time sequence constraint condition; and generating a circuit layout of the target integrated circuit based on the gate-level net list corresponding to the function block with the highest level. According to the invention, the efficiency of converting the behavior level description circuit and / or the register conversion level circuit into the gate level circuit is improved through a low-to-high comprehensive method.

Description

technical field [0001] The present disclosure relates to the technical field of integrated circuits, and in particular, to a circuit layout generation method, device, computer equipment, and storage medium. Background technique [0002] The design steps of an integrated circuit usually include: generating a behavior-level description, generating a register transfer level circuit (Register Transfer Level, RTL) description, converting a behavior-level description or RTL-level description into a gate-level netlist, and generating a physical Layout (integrated circuit layout). [0003] The current method of converting a behavior-level description or an RTL-level description into a gate-level netlist has a problem of low efficiency. Contents of the invention [0004] Embodiments of the present disclosure at least provide a method, device, computer equipment, and storage medium for generating a circuit layout. [0005] In the first aspect, an embodiment of the present disclosu...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/327G06F30/337G06F111/04
CPCG06F30/327G06F30/337G06F2111/04
Inventor 梁新理陈文杰
Owner 上海阡视科技有限公司