Bus interface debugging control method and device by adopting response mechanism

Abstract

The invention discloses a bus interface debugging control method by adopting a response mechanism. The method comprises the following steps: S1, when a to-be-debugged interface is debugged, detecting target return signals returned to a host in a bus, wherein the target return signals comprises a first return signal sent from a preset address and/or a second return signal of a preset type; S2, when the first return signal or the second return signal is detected, controlling and adjusting data content in a SYNC synchronization beat in the detected signals to be preset response information, so as to switch to reply the preset response information to the host. According to the method and the device, interface debugging faults in a response mechanism bus can be reduced, and the interface debugging efficiency, safety and reliability are improved.

Description

technical field [0001] The invention relates to the technical field of bus debugging, in particular to a method and device for controlling interface debugging in a bus using a response mechanism. Background technique [0002] In a complex industrial environment, it is required that the fieldbus can communicate correctly, quickly and stably, so as to ensure that the industrial control system can not only obtain timely and accurate field data, but also issue execution commands quickly and accurately after efficient processing. The response mechanism, that is, feedback control, is that after the sender sends data to the receiver, the receiver needs to return an ACK (receipt) to the sender. Due to the unreliability of the communication process, the transmitted data will inevitably appear in various situations such as loss, delay, error, and repetition. The response mechanism can solve such problems. Therefore, in a bus with an acknowledgment mechanism, the reliability of bus co...

AI Technical Summary

Problems solved by technology

[0005] 1. When debugging the LPC interface in the LPC bus, if there is an address but there is no storage content in the address, if the device accesses the address, it will return to a fixed full-high state, and when it returns to the full-high state, part of the processing The device platform will directly report the synchronization exception, resulting in system operation failure; or if the SYNC synchronization beat of the LPC interface returns 1111 (not the synchronization data stipulated in the protocol), it may also cause SOC operation failure

[0006] 2. When debugging the IIC interface on the IIC bus, if the BMC (Baseboard Manager Controller) of the device is not configured correctly due to hardware, software, etc., the device will not respond or reply to the wrong synchronization data during the communication process, and if the device No response, that is, no ACK response, will also lead to system failure; if the IIC interface returns NACK (deny response), it may cause the need to reset the controller, resulting in the need to perform operations such as reset and affect system debugging efficiency

[0007] 3. In other buses such as TCP (Transmission Control Protocol), PCIe (Interconnection of External Devices), etc., similarly, when the above-mentioned situations of returning non-protocol-specified synchronous data, wrong synchronous data, or equipment not responding, etc., or debugging During the process, the slave frequently replies errors to the master, which may also cause the system to run abnormally or need to perform operations such as reset, which will affect the efficiency of debugging.

[0008] In the process of system-level debugging, there will be various response situations. For example, the above-mentioned device BMC (Baseboard Manager Controller) is not properly configured due to hardware, software, etc., which will cause the device to not respond or reply to the wrong one during the communication process. Synchronous data, etc., while the return value in the traditional response mechanism is fixed, if the device does not respond or returns wrong synchronous data during the debugging process, it may affect the normal execution of the debugging or even cause a fault, such as the slave frequently replies to the master error As a result, the interface controller fails, and the device needs to be restarted frequently during the debugging process. This will not only affect the safety and reliability of debugging, but also greatly reduce the efficiency of debugging.

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