Fractional frequency division ratio phase-locked loop

Abstract

The invention discloses a fractional-type frequency dividing ratio phase-locked loop, and the phase-locked loop comprises a voltage-controlled oscillator which provides a plurality of oscillation clock signals of different phases; a fractional frequency divider which comprises a multi-analog-to-digital frequency divider which is connected with the voltage-controlled oscillator so as to receive the first oscillation clock signal and provide a first frequency-divided clock signal; a phase rotator which is used for sampling the first frequency division clock signal based on the plurality of oscillation clock signals to obtain a plurality of sampling signals; and a phase interpolator which receives two sampling signals with adjacent phases as a first threshold signal and a second threshold signal, wherein linear interpolation is carried out between the first threshold signal and the second threshold signal to obtain a second frequency division clock signal, and the working frequency of the phase interpolator is lower than that of the voltage-controlled oscillator. According to the fractional frequency divider, frequency division is carried out on the first frequency division clock signal provided by the multimode frequency divider based on the phase rotator and the phase interpolator, the fractional frequency divider with higher resolution and higher linearity can be obtained, and quantization noise of a loop is reduced.

Description

technical field [0001] The present invention relates to the technical field of integrated circuits, more specifically, to an ultra-fine fractional frequency-division ratio phase-locked loop technology. Background technique [0002] FPGA (Field Programmable Gate Array, editable logic gate array) is a semi-custom integrated circuit in the field of ASIC (Application Specific Integrated Circuit, application specific integrated circuit). field has been widely used. However, the frequency spectrum components of digital signals and clock signals in FPGA contain high-order harmonics, and the signal itself and its multiple harmonics will generate electromagnetic interference (EMI) within and between electronic systems. At present, by designing a spread spectrum clock generation circuit inside the FPGA, frequency modulation is performed on the clock signal within a certain frequency range to make the frequency of the clock signal jitter and reduce electromagnetic interference (EMI). ...

AI Technical Summary

Problems solved by technology

For fractional frequency divider technology, if the frequency divider accuracy is not high, the effect of suppressing quantization noise is not good

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