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Multi-path parallel data sampling system and method

A data sampling and data technology, which is used in electrical digital data processing, special data processing applications, instruments, etc., can solve the problems of insufficiency of synchronization and timing, and achieve the goal of reducing design cost, increasing clock frequency, and increasing bit width. Effect

Pending Publication Date: 2020-10-13
成都博宇利华科技有限公司
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  • Summary
  • Abstract
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  • Claims
  • Application Information

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Problems solved by technology

[0003] The purpose of the present invention is to provide a multi-channel parallel data sampling system and method, which is used to solve the problem that the synchronization and timing cannot be satisfied in the method of simultaneously transmitting multiple signal data in the prior art

Method used

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  • Multi-path parallel data sampling system and method

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Embodiment 1

[0021] Such as figure 1 As shown, a multi-channel parallel data sampling system includes 16-channel data parallel input and processing units, and the processing units include cascaded primary processing units, secondary processing units, tertiary processing units, and quaternary processing units. The first-level processing unit includes 8 units; the second-level processing unit includes 4 units, each of which includes two caches and a second-level engine; the third-level processing unit includes 4 units, each of which includes two There are three caches and a three-level engine, and one unit in the four-level processing unit includes two caches and a four-level engine. In each unit, the bandwidth of the engine is greater than or equal to the sum of the data bandwidth of its read cache.

[0022] The cache of each unit in the first-level processing unit is used to write one input data, and supports ping-pong operation. The first-level engine includes MUX and arbitrator. The arbi...

Embodiment 2

[0028] A multi-channel parallel data sampling method, comprising:

[0029] Step S100: input the 16 channels of data in pairs into a first-level processing unit;

[0030] Step S200: two channels of data are respectively written into two caches in the unit, and the data engine monitors the status of the caches. When a cache meets the data reading condition, the arbiter controls the MUX to select the cache and read the cached data;

[0031] Step S300: the data engine aggregates the read two cached data into one data output;

[0032] Step S400: Step S200 is executed sequentially from the second-level processing unit to the fourth-level processing unit. Finally, the fourth-level processing unit outputs the integrated data, and the bandwidth of the data engine of the subsequent level processing unit is ≥ 2 times that of the previous level of processing The bandwidth of the data engine of the unit, the number of units of the subsequent processing unit = the number of units of the pr...

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Abstract

The invention discloses a multi-path parallel data sampling system, which comprises a multi-path data parallel input and processing unit, the processing unit comprises a first-stage processing unit, asecond-stage processing unit,..., and a Y-stage processing unit which are cascaded, Y is greater than or equal to 2, and Y is a positive integer; each stage of processing unit comprises a unit consisting of a plurality of caches and a data engine; the data engine comprises an MUX and an arbiter, the arbiter monitors the data states of the caches, when one cache meets a data reading condition, thearbiter controls the MUX to gate the cache, read data and aggregate multiple outputs of the caches into one path of data output, and the bandwidth of the data engine is greater than or equal to the sum of the bandwidths of multiple paths of input data. The invention further discloses a multi-path parallel sampling method, the collection of multi-path data is realized on one chip, and dozens of paths or even hundreds of paths of parallel data sampling is realized. No matter in FPGA or ASIC design, a circuit structure with a good time sequence can be generated.

Description

technical field [0001] The invention relates to the technical field of electronic measurement, in particular to a multi-channel parallel data sampling system and method. Background technique [0002] In signal processing and data sampling systems, it is necessary to transmit multiple signal data at the same time to facilitate signal analysis. Existing common way is: one, do multiplexer (MUX) on FPGA to realize, and this way along with data bit width, clock frequency, and the raising of data way number, face in function and FPGA layout and wiring Many deficiencies: First of all, in terms of function, the data MUX is a time-division multiplexing circuit, which can only allow one channel of data to pass through at any time, which cannot guarantee the synchronization of multi-channel data sampling. In the case of very high accuracy of data synchronization, Furthermore, if the signal data bit width is large or the clock frequency is high, it will have a great impact on the combi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F30/347G06F30/392G06F30/3953
CPCG06F30/347G06F30/392G06F30/3953
Inventor 丁亮
Owner 成都博宇利华科技有限公司
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