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Front-end sampling circuit with buffer

A sampling circuit and buffer technology, applied in electrical components, analog-to-digital converters, code conversion, etc., can solve the problems of overloading the buffer and affecting the sampling linearity, to meet the power consumption, improve the sampling linearity, Guaranteed effect of sampling impedance

Pending Publication Date: 2021-12-31
NO 24 RES INST OF CETC +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0003] In view of the above existing problems in the prior art, the present invention proposes a front-end sampling circuit with a buffer, which mainly solves the problem that the existing buffer load is too heavy to affect the sampling linearity

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  • Front-end sampling circuit with buffer
  • Front-end sampling circuit with buffer
  • Front-end sampling circuit with buffer

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Embodiment Construction

[0027] Embodiments of the present invention are described below through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation modes, and various modifications or changes can be made to the details in this specification based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, in the case of no conflict, the following embodiments and features in the embodiments can be combined with each other.

[0028] It should be noted that the diagrams provided in the following embodiments are only schematically illustrating the basic ideas of the present invention, and only the components related to the present invention are shown in the diagrams rather than the number, shape and shape of the compo...

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Abstract

The invention provides a front-end sampling circuit with a buffer. The front-end sampling circuit comprises a sampling module, a bootstrap switch, a driving module, a buffer module and a bias module; the driving module comprises a first connecting end and a second connecting end, and the sampling module comprises an input end, an output end and an offset end; the buffer module comprises an input end, an output end and a third connecting end; the first connecting end is connected with one end of the bootstrap switch, and the other end of the bootstrap switch is connected with the offset end of the sampling module; the input end of the buffer module is in butt joint with an input signal, and the output end of the buffer module is respectively connected with the second connecting end, one end of the bias module and the input end of the sampling module; the third connecting end is connected with the first connecting end; and the other end of the bias module is grounded. According to the invention, the linearity of the sampling network can be effectively improved.

Description

technical field [0001] The invention relates to the field of analog integrated circuits, in particular to a front-end sampling circuit with a buffer. Background technique [0002] The existing technology either adopts a switched capacitor sample-and-hold structure, or adopts a switched capacitor hold structure with a buffer at the front end. Both of these methods need to be designed with a bootstrap switch structure. If you look at it, you will see additional bootstrap capacitors, as well as sampling capacitors, which will increase the difficulty of input driving. A bootstrap switching circuit with a front-end buffer, on the other hand, sees a bootstrap capacitor and sampling capacitor at the output of the buffer, which will load the buffer and affect the linearity of the sampling network. In order to reduce the size of the driving capacitance seen by the input buffer and improve the linearity of the buffer input tube, the present invention adopts an additional bias network...

Claims

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Application Information

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IPC IPC(8): H03M1/12
CPCH03M1/1245
Inventor 邓民明刘涛王旭吴雪美
Owner NO 24 RES INST OF CETC
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