Bandgap reference voltage generating circuit

Abstract

In a bandgap reference voltage generating circuit having first, second and third unitary circuits connected in parallel between a power supply voltage and a ground, there is added a fourth unitary circuit including an n-channel FET turned on in response to a bias voltage applied to a gate of the n-channel FET. The second unitary circuit is connected to the fourth unitary circuit through a capacitor having one end connected to a drain of the n-channel FET. When the bias voltage is applied to turn on the n-channel FET of the fourth unitary circuit, since the potential of the one end of the capacitor is dropped, a gate potential of n-channel FETs included in the first and second unitary circuits and operating in a weak inversion condition quickly becomes definite, so that a reference voltage can be generated quickly.

Description

technical field [0001] The present invention generally relates to a bandgap reference voltage generating circuit, and particularly relates to a bandgap reference voltage generating circuit with improved response speed. Background technique [0002] In the prior art, since a stable reference voltage is required to drive integrated circuits or other electronic devices, a bandgap reference voltage generating circuit is often used. Referring to FIG. 1, an example of a prior art bandgap reference voltage generating circuit is shown. [0003] The prior art bandgap reference voltage generating circuit as shown in FIG. 1 includes first, second and third unit circuits 1A, 2A and 3A to which a power supply voltage Vdd is loaded to cause the first and second unit circuits to pass through The n-channel field effect transistors (FETs) N1 and N2 of 1A and 2A operate in a weak inversion state to generate a reference voltage Vo determined by the energy band structure of the semiconductor. ...

AI Technical Summary

Problems solved by technology

[0005] However, there is a problem in the bandgap reference voltage generating circuit of the above-mentioned prior art, that is, when the power supply is just turned on, the gate potential of each FET is uncertain, and as a result, a stable reference voltage Vo cannot be quickly obtained.

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