ZYNQ-based multi-channel DAC reference clock rapid synchronization system

Abstract

The invention discloses a ZYNQ-based multi-channel DAC reference clock rapid synchronization system, and relates to the technical field of multi-channel DAC reference clock synchronization. The system comprises a ZYNQ chip, at least one clock buffer chip, and a plurality of DAC chips, wherein the PL end and the PS end of the ZYNQ chip are interconnected through an AXI bus, the clock buffer chip is configured to generate a clock, the DAC chip is configured to work when a sampling clock is looped back to the PL end of the ZYNQ chip, the PL end of the ZYNQ chip performs phase detection and phase processing on multiple paths of reference clock signals to obtain delay output configuration parameters of the clock buffer chip, and the delay output configuration parameters are transmitted to the PS end through the AXI bus; compared with a traditional FPGA chip, the ZYNQ chip reduces the use of logic resources of the FPGA under the cooperation of the PS end and the PL end; when the working states of the clock buff chip and the DAC chip need to be changed, only the PS end of the ZYNQ chip needs to be changed, so that debugging and testing of technicians are greatly facilitated.

Description

technical field [0001] The invention relates to the technical field of reference clock synchronization of multiple DACs, in particular to a ZYNQ-based fast reference clock synchronization system of multiple DACs. Background technique [0002] In transmitter applications, especially in transmitter applications where DAC is used for I\Q upconverter or digital beamforming, the same-source and in-phase design of data clock provided to DAC is used for data source synchronization; especially for digital In the beamforming transmitter, it is necessary to accurately control the relative phase between a large number of DACs; therefore, in actual engineering implementation, the synchronization design of the reference clock network of multiple DACs is the basis for the realization of the functional indicators of the entire transmitter. [0003] In the prior art, when the traditional ARM+FPGA architecture is used to synchronize the reference clock network of multiple DACs, the tradition...

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Problems solved by technology

[0004] The purpose of the present invention is: in order to solve the traditional ARM+FPGA architecture used for multi-channel DAC reference clock network synchronization, the traditional FPGA logic resource occupancy rate is high, the amount of calculation of logic resources is large, when debugging multi-channel DAC phase synchronization When debugging traditional FPGA projects, it is necessary to re-layout and wire, and the technical problems of long debugging time. The present invention provides a fast synchronization system for reference clocks of multi-channel DACs based on ZYNQ

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