Semiconductor memory devices

A semiconductor and memory technology, applied in the field of three-dimensional semiconductor memory devices, can solve problems such as limited integration

Pending Publication Date: 2022-02-18
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Since the degree of integration of a two-dimensional (2D) semiconductor memory device of the related art is mainly determined based on the area occupied by a unit memory cell, although the degree of integration of a 2D semiconductor memory device has increased, the degree of integration is still limited

Method used

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  • Semiconductor memory devices
  • Semiconductor memory devices
  • Semiconductor memory devices

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Embodiment Construction

[0018] Figure 1A to Figure 20C is a diagram illustrating a method of manufacturing a semiconductor memory device according to an embodiment. in detail, Figure 1A , Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A , Figure 10A , Figure 11A , Figure 12A , Figure 13A , Figure 14A , Figure 15A , Figure 16A , Figure 17A , Figure 18A , Figure 19A and Figure 20A are shown respectively along the Figure 1B and Figure 1C , Figure 2B and Figure 2C , Figure 3B and Figure 3C , Figure 4B and Figure 4C , Figure 5B and Figure 5C , Figure 6B and Figure 6C , Figure 7B and Figure 7C , Figure 8B and Figure 8C , Figure 9B and Figure 9C , Figure 10B and Figure 10C , Figure 11B and Figure 11C , Figure 12B and Figure 12C , Figure 13B and Figure 13C , Figure 14B and Figure 14C , Figure 15B and Figure 15C , Figure 16B and Figure 16C , Figure 17B and Figu...

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Abstract

A semiconductor memory device includes a word line extending in a vertical direction on a substrate, a channel layer surrounding the word line to configure a cell transistor and having a horizontal ring shape with a predetermined horizontal width, a bit line disposed at one end of the channel layer in a first horizontal direction and extending in a second horizontal direction perpendicular to the first horizontal direction, and a cell capacitor disposed at other end of the channel layer in the first horizontal direction, the cell capacitor including an upper electrode layer extending in the vertical direction, a lower electrode layer surrounding the upper electrode layer, and a capacitor dielectric layer disposed between the upper electrode layer and the lower electrode layer.

Description

[0001] This application is based on, and claims priority from, Korean Patent Application No. 10-2020-0097541 filed with the Korean Intellectual Property Office on Aug. 4, 2020, the disclosure of which is hereby incorporated by reference in its entirety. technical field [0002] The disclosed embodiments relate to a semiconductor memory device, and in particular, to a three-dimensional (3D) semiconductor memory device. Background technique [0003] In order to meet the demands of miniaturization, multi-function and high-performance electronic products, high-capacity semiconductor memory devices are required, and in order to provide high-capacity semiconductor memory devices, increased integration is required. Since the degree of integration of a related art two-dimensional (2D) semiconductor memory device is mainly determined based on the area occupied by a unit memory cell, although the degree of integration of the 2D semiconductor memory device increases, the degree of integ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/108H01L27/06
CPCH01L27/0688H10B12/315H10B12/50H10B12/30H10B12/03H10B12/05H10B12/488H01L28/40H10B12/31G11C7/18G11C8/14H10B43/27H10B41/10H10B41/27H10B41/35H10B43/10H10B43/35
Inventor 李炅奂金容锡金炫哲徐亨源柳成原洪载昊
Owner SAMSUNG ELECTRONICS CO LTD
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