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Memory device

A memory and memory unit technology, applied in static memory, read-only memory, digital memory information, etc., can solve the problems of semiconductor device size reduction, complex wiring layout, etc.

Pending Publication Date: 2022-02-22
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

According to the increase in the integration of memory devices and the development of process technology, the demand for reducing the size of the page buffer may lead to a reduction in the size of the semiconductor device, and therefore, the layout of the wiring connected to the semiconductor device may become complicated

Method used

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Embodiment Construction

[0030] Hereinafter, embodiments of the inventive concept will be described in detail with reference to the accompanying drawings.

[0031] figure 1 is a block diagram of a memory device 10 according to example embodiments of the inventive concepts.

[0032] refer to figure 1 , the memory device 10 may include a memory cell array 100 and a peripheral circuit 200 . According to example embodiments, the peripheral circuit 200 may include a page buffer circuit 210 , a control circuit 220 , a voltage generator 230 and a row decoder 240 . According to example embodiments, the peripheral circuit 200 may further include a data input-output circuit, an input-output interface, and the like.

[0033] The memory cell array 100 may be connected to the page buffer circuit 210 through a bit line BL, and may be connected to a row decoder 240 through a word line WL, a string selection line SSL, and a ground selection line GSL. The memory cell array 100 may include a plurality of memory cel...

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Abstract

A memory device is described. The memory device includes: a memory cell array including a plurality of memory cells; and a page buffer circuit provided in a page buffer region including a main region and a cache region provided in a first horizontal direction, and including a first page buffer unit and a second page buffer unit adjacent to each other in a second horizontal direction in the main region. A first sensing node of the first page buffer unit includes a first lower metal pattern, and a first upper metal pattern, and electrically connected to the first lower metal pattern. A second sensing node of the second page buffer unit includes a second lower metal pattern, and a second upper metal pattern, electrically connected to the second lower metal pattern, and not adjacent to the first upper metal pattern in the second horizontal direction.

Description

[0001] Cross References to Related Applications [0002] This application is based on and claims priority from Korean Patent Application No. 10-2020-0100118 filed with the Korean Intellectual Property Office on August 10, 2020, the disclosure of which is incorporated herein by reference in its entirety. technical field [0003] The inventive concept relates to memory devices, and more particularly, to page buffer circuits and memory devices including the same. Background technique [0004] Recently, communication devices having multiple functions and handling a large amount of information have been developed, and therefore, memory devices have been required to have a large capacity and be highly integrated. A memory device may include a page buffer to store data in or output data from a memory cell, and the page buffer may have semiconductor devices such as transistors. According to the increase in the integration level of memory devices and the development of process techn...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C5/06G11C7/10G11C16/04H01L27/11573H01L27/11582
CPCG11C5/06G11C7/1057G11C7/1084G11C16/0483H10B43/40H10B43/27G11C5/10G11C7/02G11C16/26G11C2207/105G11C2216/02G11C2216/30G11C5/025H10B41/27H01L27/0207G11C16/10H01L23/528H10B41/40G06F3/0656H10B43/35
Inventor 曹溶成姜仁昊朴安洙朴曾焕申东夏郑在元
Owner SAMSUNG ELECTRONICS CO LTD