rocc coprocessor interface model and its automatic generation tools and implementation methods

Abstract

The invention discloses a ROCC coprocessor interface model and its automatic generation tool and implementation method, including: an instruction analysis module, an instruction storage unit, an input data storage, a calculation result storage, a read-in data state machine module, and an interface behavior state machine module; the instruction analysis module is connected to the ROCC coprocessor; the input data memory and the calculation result memory are both connected to the memory L1 cache. Automatic generation tools include: interface generation function implementation and interface generation main function; first generate ROCC coprocessor interface files and instruction header files for user testing, and then integrate ROCC coprocessors into RISC‑V systems to realize ROCC coprocessors Generation of processor interface models. By adopting the technical scheme of the present invention, the specific implementation details of RISC-V instructions and ROCC interfaces can be simplified and shielded, and a hardware interface adapted to the coprocessor can be quickly generated.

Description

technical field [0001] The present invention relates to the RTL interface technology of the RISC-V architecture extension accelerator kernel, in particular to a Rocket Custom Coprocessor (Rocket Custom Coprocessor, ROCC) interface model, an interface model automatic generation method and tool, including hardware control of the ROCC extended instruction protocol An interface automatic generation tool and an implementation method of a device, a software emulator, and a RISC-V code generation project with an accelerator. Background technique [0002] Chipyard is an open source framework for agile development of Chisel generator-based System-on-Chip (SoC). Chipyard was developed by Berkeley Architecture Research (UCB-BAR) at the University of California, Berkeley (UCB). It allows the generation of RISC-V SoCs with everything from MMIO-mapped peripherals to custom accelerators utilizing the Chisel Hardware Construction Language, Rocket Chip SoC Generator, and other UCB-BAR proje...

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Problems solved by technology

[0004] Although these projects have been successfully integrated into the Chipyard open source framework and connected to the RISC-V core with the ROCC coprocessor interface, there are great differences in the interfaces of each project

If a developer designs a custom accelerator, in order to test the performance of the accelerator, and wants to connect to the RISC-V core Rocket with the ROCC coprocessor interface, it is necessary to design an interface suitable for the custom accelerator. The developer must understand the ROCC I have a detailed understanding of the characteristics of the interface, but this process is difficult for developers who are not familiar with RISC-V instructions, and designing a hardware interface suitable for their own accelerator from scratch also greatly increases the time overhead

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