Semiconductor integrated circuit

Abstract

The invention is to obtain a semiconductor integrated circuit having a plurality of integrated circuit blocks for realizing a specified function in which function test is performed efficiently for all integrated circuit blocks while suppressing lowering in the operating speed of circuit in normal mode and test mode. Since the signal transmission path between integrated circuit blocks is not provided with a flip-flop circuit, a random logic circuit, or the like, but only multiplexers are provided, respectively, between the first output terminal of the circuit block and the first input terminal of the circuit block and between the second output terminal of the circuit block and the second input terminal of the circuit block, signal delay is suppressed.

Description

Technical field [0001] The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit that improves the efficiency of functional operation testing of a plurality of integrated circuit blocks that realize predetermined functions. Background technique [0002] In recent years, due to the progress of large-scale semiconductor integrated circuits, integrated circuit blocks that realize various functions can be loaded in a variety of loading methods in semiconductor integrated circuits. These integrated circuit blocks are connected to each other to realize the function as a semiconductor integrated circuit. These semiconductor integrated circuits are equipped with multiple input terminals and multiple output terminals for interfacing with the outside. [0003] In addition, the integrated circuit block is also provided with a plurality of input wirings and a plurality of output wirings for interconnection within the semi...

AI Technical Summary

Problems solved by technology

[0025] The first problem in the above-mentioned conventional semiconductor integrated circuit 1d is that, in the normal mode, since a flip-flop circuit is inserted in the input path from the integrated circuit block 81 to the integrated circuit block 82, the input path from the integrated circuit block 81 to the integrated circuit block The input of the 82 must implement timing synchronous with the clock, so that the operation speed of the normal mode is slow

[0026] The second problem is that in the normal mode, since a flip-flop is inserted in the output path from the integrated circuit block 82 to the integrated circuit block 83, a delay is generated in the output from the integrated circuit block 82 to the integrated circuit block 83, so that slow motion

[0027] The third problem is that in the test mode of the integrated circuit block 82, since a plurality of multiplexers are inserted between the flip-flop circuits constituting the shift register, a delay is generated on the path constituting the shift register, slow down

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