Logic IP core for expanding parallel interface

A logic and interface technology used in the field of embedded systems

Pending Publication Date: 2022-04-12
中航洛阳光电技术有限公司
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the processor does not have the traditional Local Bus interface of airborne equipment, and the interfaces of mature processor peripheral domestic devices such as FLASH, Nvram and other memories, as well as RS422, SSI, synchronous differential, LVDS and other system control circuits are all LocalBus interfaces

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  • Logic IP core for expanding parallel interface

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Embodiment Construction

[0016] The present invention will be further described below in conjunction with the accompanying drawings and embodiments.

[0017] A logic IP core used to expand the parallel interface of the domestic Feiteng processor (FT-2000 / 4), read the shift-in register and shift-out register in the logic IP through the SPI interface of the domestic Feiteng processor (FT-2000 / 4) Write and corresponding timing control to realize the conversion between SPI interface and Local Bus interface;

[0018] Through the SPI interface of the domestic Feiteng processor (FT-2000 / 4), the command shift-in register and the data shift-out register are controlled. The first operation realizes the transmission of the write command and address, and the second operation realizes the transmission of the written data. , to complete the writing operation of the Local Bus interface device and the interface logic IP based on the Local Bus;

[0019] Through the SPI interface of the domestic Feiteng processor (FT-...

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Abstract

The invention provides a logic IP (Internet Protocol) core for expanding a parallel interface, which is characterized in that a 32-bit command address shift-in register, a 16-bit data shift-out register and a 16-bit data shift-in register are instantiated in logic; a chip selection signal SPICS and a data output signal SPIMOSI of an SPI interface of the processor are connected to a command and address shift-in register of a write-in logic and a read logic and a data shift-out register of the write-in logic, and a data input signal SPIMISO of the SPI interface is connected to a data shift-in register of the read logic. Wherein the command address shift-in register, the data shift-out register and the data shift-in register combine read-write commands, addresses and data according to agreed protocol frames. According to the invention, the problem that the domestic Feiteng processor cannot be directly connected with the Local Bus interface equipment and the interface logic IP based on the Local Bus is solved, and the installation and use of the mature domestic Local Bus interface equipment and the interface logic IP are realized.

Description

technical field [0001] The invention relates to the technical field of embedded systems, in particular to a logical IP core for extending parallel interfaces. Background technique [0002] The core processing and computing platform is the data computing center and service center of the aircraft mission system, providing highly reliable, high-safety real-time computing services and high-performance data processing services for the mission system. Among them, the domestic high-performance embedded processor is the core of the equipment. With the trend of 100% self-controllable airborne equipment and high-performance requirements, the domestic high-performance embedded processor FT-2000 / 4 of Tianjin Feiteng Company has become the core Processor of choice for computing platforms. [0003] Tianjin Feiteng's FT-2000 / 4 adopts 16nm processing technology, built-in four 64-bit processor cores FTC663, the main frequency can reach 2.2GIPS, supports single / double-precision hard floating...

Claims

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Application Information

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IPC IPC(8): G06F13/42
CPCY02D10/00
Inventor王亚辉杨改赞周明杰刘伟超
Owner中航洛阳光电技术有限公司