Memory cell and semiconductor device having the same

Abstract

The present disclosure provides a semiconductor device including: a memory cell array including a plurality of memory cells vertically stacked on a base substrate, where each memory cell includes: a bit line vertically oriented with respect to the base substrate; a capacitor laterally spaced apart from the bit line; an active layer laterally oriented between the bit line and the capacitor; a word line on any one of an upper surface and a lower surface of the active layer and extending laterally in a direction crossing the active layer; and a bit line discharge portion coupled to the bit line.

Description

[0001] Cross References to Related Applications [0002] This application claims priority from Korean Patent Application No. 10-2020-0133521 filed on October 15, 2020, the entire contents of which are hereby incorporated by reference. technical field [0003] Various embodiments of the present invention relate to a semiconductor device, and more particularly, to a memory cell and a semiconductor device including the memory cell. Background technique [0004] Recently, in order to increase the net die of a memory device, the size of a memory cell has been continuously reduced. As the size of memory cells becomes finer, parasitic capacitance must be reduced and capacitance must be increased, but net die increase is difficult due to structural limitations of memory cells. Contents of the invention [0005] Embodiments of the present invention relate to a highly integrated memory cell and a semiconductor device including the highly integrated memory cell. [0006] According ...

AI Technical Summary

Problems solved by technology

As memory cell size becomes finer, parasitic capacitance must be reduced and capacitance must be increased, but net die gain is difficult due to memory cell structural limitations

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