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Chip verification IP device and test method thereof

A test method and chip technology, applied in the direction of measuring devices, electronic circuit testing, measuring electricity, etc., can solve problems such as lack of advantages, and achieve the effect of saving labor costs, good adaptability, and easy modification and upgrade.

Active Publication Date: 2022-04-22
ZHEJIANG UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

But the disadvantage of this method is also obvious, that is, the company's products will not have their own unique advantages in the long run, and tend to be the same as other companies' products in terms of characteristics and parameters

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  • Chip verification IP device and test method thereof
  • Chip verification IP device and test method thereof
  • Chip verification IP device and test method thereof

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Embodiment Construction

[0050] The present invention will be described below in conjunction with the accompanying drawings and embodiments.

[0051] The invention discloses a chip verification IP device and a testing method thereof.

[0052] 1. Chip Verification IP

[0053] Chip verification IP includes the unit component (agent) of the master (master), the unit component (slave) or the system environment of the slave side (slave), and the independent unit unit needs to have a driver (driver), a monitor (monitor) and a sequencer (sequencer) .

[0054] In order to be able to realize many functions of VIP, we need to define a complete unit components of VIP, and the environment structure that they constitute can realize self-test. The unit components of VIP can be divided into master unit components and slave unit components according to the standard bus protocol, which respectively act as the master and slave of the standard bus in the verification environment; figure 1 As shown, the unit component...

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Abstract

The invention discloses a chip verification IP device and a test method thereof. The verification IP comprises a master end unit component, a slave end unit component or a system environment, and can realize the following functions: providing a verification plan for a corresponding bus protocol, the verification plan comprising a port signal upset rate, a check coverage rate and a function coverage rate; a plurality of predefined event triggers are built in; a callback function capable of modifying behaviors of the driver and the monitor is included; the excitation of insertion errors is supported; the test sequence comprises a predefined test sequence; and performing unit component testing and system environment testing by using the VIP testing environment and the configuration item. According to the invention, the VIP which can be integrated in the chip UVM verification environment is developed, and then the VIP is utilized to test and monitor the corresponding bus interface of the chip to be tested.

Description

technical field [0001] The invention belongs to the field of chip verification testing, and in particular relates to a chip verification IP device and a testing method thereof. Background technique [0002] In the chip design and development process, it is necessary to provide a stable verification environment to test each module of the chip and the entire system. In the verification process, the unit components used to build the entire test platform are called chip verification IP (VIP, Verificatioin Intellectual Properties). The role of the verification IP is to play the role of interacting with the designed interface. Through sufficient stimulus testing and monitoring of the design, the function of the design is analyzed and checked, and then ensure that each module of the chip and the entire system are in compliance with Various functional requirements. [0003] Like design IP (Design IP), chip verification IP also needs to be developed and tested. Only after a comple...

Claims

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Application Information

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IPC IPC(8): G01R31/28G06F30/33
CPCG01R31/2851G01R31/2868G06F30/33G06F2115/08G06F2111/08
Inventor 刘斌虞小鹏谭年熊
Owner ZHEJIANG UNIV