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Convolutional neural network accelerator based on FPGA

A convolutional neural network and accelerator technology, applied in the field of convolutional neural network accelerators, to achieve the effects of optimizing energy efficiency ratio, ensuring real-time performance and stability, and low power consumption

Pending Publication Date: 2022-04-22
BEIJING INST OF COMP TECH & APPL
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  • Application Information

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Problems solved by technology

[0004] The technical problem to be solved by the present invention is: how to design a convolutional neural network accelerator, and at the same time solve the problem of the speed and energy consumption of the convolutional operation processor

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  • Convolutional neural network accelerator based on FPGA
  • Convolutional neural network accelerator based on FPGA
  • Convolutional neural network accelerator based on FPGA

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Embodiment Construction

[0032] In order to make the purpose, content, and advantages of the present invention clearer, the specific implementation manners of the present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments.

[0033] In order to solve the speed and energy consumption problems of the convolution operation processor at the same time, accelerate the convolution operation, and reduce hardware power consumption, the present invention provides an FPGA-based convolution neural network accelerator, which optimizes the energy efficiency ratio of the hardware and ensures the target The real-time and stability of detection tasks.

[0034] like figure 1 Shown, a kind of FPGA-based convolutional neural network accelerator provided by the present invention comprises:

[0035] (1) Host: responsible for the management of slave devices composed of other modules in the accelerator, sending input image data and weight parameters to the PCIE D...

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Abstract

The invention relates to a convolutional neural network accelerator based on an FPGA, and belongs to the technical field of target detection. In the method, the convolutional neural network accelerator is designed to comprise a host used for sending input image data and weight parameters to a PCIE DMA module and receiving an output result from the PCIE DMA module; and the operation module is used for performing convolution, pooling and logistic regression operation on the image data input from the image data caching module and the weight parameters from the weight data caching module. Through the design of the accelerator, the energy efficiency ratio of hardware is optimized, and the real-time performance and stability of a target detection task are ensured.

Description

technical field [0001] The invention belongs to the technical field of target detection, and in particular relates to an FPGA-based convolutional neural network accelerator. Background technique [0002] At present, in the target detection technology based on the convolutional neural network, the convolution operation is usually delivered to the CPU or GPU for processing. The CPU core can only process computing tasks serially, even if the multi-core CPU has a low degree of parallelism, the speed of the CPU for convolution calculation is relatively low. There are a large number of multiplication and addition units inside the GPU, which can process convolution operations very quickly, but its power consumption is also very large, which is not suitable for performing edge-end reasoning tasks. Contents of the invention [0003] (1) Technical problems to be solved [0004] The technical problem to be solved by the present invention is: how to design a convolutional neural net...

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06N3/04G06F13/38G06F13/42G06F3/06
CPCG06F13/4221G06F13/385G06F3/0656G06N3/047G06N3/045
Inventor 张红磊聂煜桐侯运通沈月峰龚清生王吕大
Owner BEIJING INST OF COMP TECH & APPL
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