A method, device, CPU chip and server for reducing on-chip network power consumption

Abstract

The embodiments of the present invention disclose a method, a device, a CPU chip and a server for reducing the power consumption of an on-chip network, which relate to the technical field of computers and can effectively reduce the power consumption of the on-chip network. The method includes: acquiring working status data of the network-on-chip NoC, the working status data including one of the maximum number of caches used in the NIU in the most recent period of time, the maximum number of caches used in the RU in the most recent period of time, or According to the working status data, calculate the number of caches that need to be opened in the NIU and RU respectively; and close the remaining number of caches in the NIU and RU according to the number of caches that need to be opened. The present invention is suitable for the occasion of reducing the power consumption of the on-chip network.

Description

technical field [0001] The present invention relates to the field of computer technology, and in particular, to a method, a device, a CPU chip and a server for reducing the power consumption of an on-chip network. Background technique [0002] With the development of integrated circuits and the improvement of processes, the integration degree of chips is constantly improving, and large-scale SOC (System on Chip, system-on-chip) design has become the mainstream. NoC (Network on Chip, Network on Chip) is used to realize the on-chip interconnection of various devices in the SOC. It mainly includes multiple Network Interface Units (NIUs) and Router Units (RUs), such as figure 1 As shown, the NIU is at the boundary of the NoC, and each NIU is used to connect a mounted device and is responsible for managing all requests issued by the device and all requests sent to the device. For each request sent by the device, the NIU records the relevant information and forwards it to the RU....

AI Technical Summary

Problems solved by technology

However, considering that it will take a long time to restore the NoC as a whole from the power-off state to the working state, in order to ensure the performance of the system, there are more requirements for the NoC as a whole to enter the power-off state during design. When the actual system is working, even if the NoC The workload is very low and there is very little chance for the NoC to be able to go into a total power down state, resulting in a lot of ineffective power consumption

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