A video compression system and server

Abstract

The invention discloses a video compression system and a server. The video compression system includes a central processing unit, a hardware detection module, a writing control module, a reading control module, and a FIFO array module. The FIFO array module includes a selection switch; the central processing unit is configured to send the first An enable signal to the hardware detection module, the read control module, and the selection switch; the selection switch is configured to select and write data to the FIFO array module through the hardware detection module based on the first enable signal; the hardware detection module is configured to be based on the first enable signal The test data is written into the FIFO array module; the read control module is configured to read the test data from the FIFO array module based on the first enabling signal and transmits it to the hardware detection module; the hardware detection module is also configured to combine the read test data with the written The test data are compared, and the compression formats supported by the video compression system are determined based on the comparison results. The solution of the invention increases the stability of the video compression function.

Description

technical field [0001] The present invention relates to the technical field of video processing, in particular to a video compression system and a server. Background technique [0002] The transmission process of the video compression system in the traditional baseboard management control chip is as follows: first, the VGA (VideoGraphics Array, video graphics array) transmits the video information of the host (HOST) to the video compression control module (Video CMP IP) for video compression, and the compression is completed. After that, the data is written to DDR (Double Data Rate, double-rate synchronous dynamic random access memory), the EMAC (network card) driver reads the compressed data, and transmits the video data to the remote (REMOTE) through the network for remote display. [0003] In the traditional solution, the video data on the host side is transmitted to the baseboard management control chip through PCIe, and the original RGB format video data is converted in...

AI Technical Summary

Problems solved by technology

[0003] In the traditional solution, the video data on the host side is transmitted to the baseboard management control chip through PCIe, and the original RGB format video data is converted to YUV (a color coding method, Y means brightness ( Luminance, Luma), U and V are data in the format of chromaticity and density (Chrominance, Chroma), and then use the on-chip storage resources for Y, U, V data (for example: RAM (Random Access Memory, random access Memory abbreviation)) for caching, according to the requirements of BLOCK (block) format conversion, 16 Y_RAM, 16 U_RAM, 16 V_RAM are required. The disadvantage of the traditional solution is that it needs to occupy a lot of on-chip resources, and 48 RAMs are required at the same time. The depth of each RAM is very deep (at a resolution of 1920*1200, the depth is set to 16384 in practice, and usually 16 RAMs of 1024 are spliced ​​together during implementation, so a total of 16*48=768 depths are required. 1024 RAM), such a large number of concentrated RAMs are placed in the chip layout, the comprehensive constraints on the back end of the chip, layout and wiring, packaging and manufacturing, etc. all cause great risks, and there are often problems with individual or multiple RAMs , For example, the data written and read is inconsistent, or even the data cannot be read. Therefore, the stability of the video compression function of the substrate management control chip integrated with the video compression function after tape-out is relatively poor, and in serious cases, there may even be data loss and image disorder. , which poses a risk of failure to the project

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