Chip packaging structure

Abstract

The invention discloses a chip packaging structure. The chip packaging structure comprises a substrate; the first chip layer is located on one side of the substrate and comprises one or more chips, and the non-functional surfaces of the chips of the first chip layer face the substrate; the first rewiring layer is positioned on one side, back to the substrate, of the first chip layer and is electrically connected with a functional surface of a chip of the first chip layer; the second chip layer is located on the side, back to the first chip layer, of the first rewiring layer and comprises one or more chips, and the functional faces of the chips of the second chip layer face the first rewiring layer and are electrically connected with the first rewiring layer; the second re-wiring layer is positioned on one side, back to the first re-wiring layer, of the second chip layer and is electrically connected with the first re-wiring layer; one end of the bonding wire is electrically connected with the second rewiring layer, and the other end of the bonding wire is electrically connected with the substrate. According to the chip packaging structure provided by the invention, longitudinal and vertical stacking of three-dimensional multiple chips can be realized, the transverse space of the substrate is saved, and the cost is saved.

Description

technical field [0001] The present application relates to the technical field of semiconductors, in particular to a chip packaging structure. Background technique [0002] The descriptions in this section only provide background information related to the disclosure in this specification and may not constitute prior art. [0003] In the packaging industry, the structure in which devices are arranged horizontally in the system-in-package is the simplest and the easiest to obtain high yield, so it is the most widely used. However, as the demand for miniaturization of packages increases, in order to further reduce the volume, chips or devices need to be stacked in the vertical direction. [0004] The 3D package is realized by stacking chips, and the interconnection after stacking can usually be realized by wire bonding or through silicon via (Through Silicon Via, TSV). TSV technology has relatively large limitations and high cost, while wire bonding is a relatively traditiona...

AI Technical Summary

Problems solved by technology

Gasket stacking and FOW methods require two bonding wires to be bonded on the same BondFinger, which requires a larger Bond Finger to be designed on the substrate, which cannot be satisfied by the existing substrate size.

At the same time, these two solutions will increase the longitudinal dimension of the entire package, and the two bonding wires on the same Bond Finger will also bring reliability risks

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