Memory device, memory system, and operating method of memory system

Abstract

The invention discloses a memory device, a memory system and an operating method of the memory system. The memory device includes a memory cell array and a test controller. The memory cell array includes a plurality of memory cells, where the memory cell array is divided into a plurality of regions. And a test controller configured to perform a parallel bit test (PBT) on the plurality of memory cells, in which the test controller selects failure data including a failure data bit among internal data output from the plurality of regions during the PBT, and outputs the failure data to the outside of the memory device via a data input / output signal line.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2020-0146316 filed on November 4, 2020 at the Korean Intellectual Property Office, the disclosure of which is hereby incorporated by reference in its entirety. technical field [0002] Embodiments of the inventive concepts relate to semiconductor memory devices, and more particularly, to memory devices capable of outputting failure data in a Parallel Bit Test (PBT) mode to support an Error Correcting Code (ECC) function and a memory system including the memory devices. Background technique [0003] Data processing systems, such as data centers, are hosted by many businesses and their computer systems. Data centers are used to distribute hosted applications and / or transactions and include networked computer resources (such as servers, disks, or virtual machines) commonly referred to as clouds. In this configuration, the enterprise is a client in the data center. Data centers provide clients with many...

AI Technical Summary

Problems solved by technology

[0008] However, when a failure is determined based on the PBT (for example, when a failure occurs as a result of a comparison operation), it may not be possible to specify the memory cell of the error bit that has caused the failure by using the output of the PBT

In this case, although the memory module has the ECC function, there is a problem that the error bit cannot be detected and corrected

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