Transmission gate design method and circuit capable of avoiding voltage jump

Abstract

The invention discloses a transmission gate design method and circuit capable of avoiding voltage jump. The method comprises the following steps: step 1, comparing IN voltage with OUT voltage; 2, if a large voltage difference exists between the OUT voltage and the IN voltage, rapidly pulling the OUT voltage to a level close to the IN voltage; step 3, further opening the transmission gate; in the step 2, the current source is pulled up or pulled down according to the requirement of the implementation circuit, namely, the OUT voltage is closer to the IN voltage; the size of the current source is determined according to the speed of opening the transmission gate; in the second step, the imbalance and speed of OUT and IN comparators are also designed according to the fact that the OUT voltage and IN voltage of a final actual circuit are equal after a transmission gate is opened, the simple current source and the comparators can solve the problem that after the transmission gate is opened, a sudden change of a control waveform is caused by redistribution of charges between capacitors, and therefore the stability of the transmission gate is improved. It is guaranteed that when the transmission door is opened, the waveform of the front face of the transmission door is in smooth transition.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a transmission gate design method and circuit that can avoid voltage jumps. Background technique [0002] In LED drive, LDO, load switch and other circuits, as the load power increases, the power tube also increases, but at the same time, low static power consumption or low current control accuracy is required. Divide and control separately. At this time, in order to avoid using more devices in series with the original device to control the power, traditional transmission gate circuits are usually used to control the gate voltage of these power tubes, such as figure 1 The traditional transmission gates shown are mainly for logic level signals and analog signals for driving small capacitors. in as figure 2 When driving large power transistors PMA and PMB, in order to avoid the gate OUT of PMA, when CTL is low and the transmission gate is disconnected, it is in a fl...

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Problems solved by technology

in such as figure 2 When driving large power transistors PMA and PMB, in order to avoid the gate OUT of PMA, when CTL is low and the transmission gate is disconnected, it is in a floating state, and PM1 needs to pull up OUT to VDD; when CTL is High, when the transmission gate is turned on, OUT will be pulled from the VDD voltage to the level equal to the IN voltage, but when OUT is pulled to the same level as IN, due to the limited drive capability of the IN input signal and The gate capacitance of the PMA is relatively large, and the IN voltage may be pulled up by OUT instead of the voltage of OUT being pulled down to equal the voltage from IN;

[0003] The reason is that due to the limitation of the driving capability of IN, the gate charge of PMB will be redistributed between the two capacitances of PMA and PMB at the moment when the transmission gate is turned on. According to the size of the gate capacitance of the two MOS transistors, It can be obtained that dVin=[1-1 / (C_PMA+C_PMB)]*C_PMA*Vin, due to this waveform jump of the gate voltage, there will be a large voltage fluctuation at the output terminal VDP of the entire power, and this voltage fluctuation, In severe cases, it will directly lead to VDP output failure

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