Methods for forming microelectronic devices with self-aligned interconnects and related devices and systems

Abstract

A method for forming a microelectronic device includes forming an interconnect that is self-aligned with both a lower conductive structure and an upper conductive structure. At least one lateral dimension of the interconnect is defined when subtracting to pattern the lower conductive structure and the first sacrificial material. At least another lateral dimension of the interconnect is defined by patterning a second sacrificial material, or by an opening formed in a dielectric material through which the interconnect is to extend. A portion of the first sacrificial material and the second sacrificial material exposed within the opening through the dielectric material are removed and replaced with a conductive material to integrally form the interconnect and the upper conductive structure. The interconnect occupies a volume between vertical overlapping regions of the lower conductive structure and the upper conductive structure, wherein such overlapping regions coincide with the opening through the dielectric material.

Description

[0001] priority claim [0002] This application claims the benefit of the filing date of US Patent Application Serial No. 16 / 653,442, filed on October 15, 2019. technical field [0003] Embodiments of the present disclosure relate to the field of microelectronic device design and fabrication. More particularly, the present disclosure relates to methods for forming microelectronic devices (eg, memory devices) having self-aligned interconnects between lower and upper conductive structures. The present disclosure also relates to devices and systems incorporating such self-aligned interconnects. Background technique [0004] Integrated circuits (ICs), key components in thousands of electronic systems, typically contain interconnected networks of electrical components (eg, semiconductor devices) fabricated on a common base or substrate. Semiconductor devices may include capacitors, resistors, transistors, diodes, or other devices, and the devices may be arranged in different l...

AI Technical Summary

Problems solved by technology

However, the dual damascene fabrication process generally does not ensure sufficient alignment (eg, physical and electrical contact) between the interconnect and the first conductive structure.

Therefore, making interconnects with reliable physical contact between the interconnects and the associated lower and upper conductive structures remains a challenge

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