Programmable device configuration memory system

Abstract

An example configuration system for a programmable device includes a configuration memory read / write unit configured to receive configuration data for storage in a configuration memory of the programmable device, the configuration memory including a plurality of frames; a plurality of configuration memory read / write controllers coupled to the configuration memory read / write units; and a plurality of fabric sub-regions (FSRs) coupled to the plurality of configuration memory read / write controllers, respectively, each FSR including a pipeline of memory cells of the configuration memory disposed between the buffers and a configuration memory read / write pipeline unit coupled between the pipeline and a next FSR of the plurality of FSRs.

Description

technical field [0001] Examples of the present invention relate generally to programmable devices, and more particularly to configuration memory systems for programmable devices. Background technique [0002] Programmable devices, such as field programmable gate arrays (FPGAs) and systems on chips (SOCs) with FPGA programmable fabrics, are gaining momentum in artificial intelligence (AI), data center, and automotive applications. In these applications, a useful technique is partial reconfiguration of programmable devices. Partial reconfiguration is the ability to dynamically modify a logic block of a programmable device by downloading a partial configuration bit file, while the remaining logic continues to operate without interruption. Partial reconfiguration performance has traditionally been limited by distributed memory systems in programmable devices, where data lines run across the entire device width and the memory controller has to wait for the previous write / read to...

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Problems solved by technology

Traditionally, partial reconfiguration performance has been limited by distributed memory systems in programmable devices, where data lines run the entire width of the device, and the memory controller has to wait for a previous write / read to complete before initiating the next write / read Pick

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