Upper computer and FPGA high-speed data transmission architecture based on UDP protocol and implementation method

Abstract

The invention discloses an upper computer and FPGA high-speed data transmission architecture based on a UDP protocol and an implementation method, an FPGA board card in the architecture comprises a 40G IP core, a data packet sending module, a data packet analysis module, a read FIFO module, a write FIFO module, a sending end FIFO and a receiving end FIFO, the 40G IP core carries out data receiving and sending with the upper computer through a 40G optical fiber and a 40G PCIe optical fiber network card, the output of the 40G IP core is connected with the data packet analysis module, and the data packet analysis module is connected with the receiving end FIFO. The output of the data packet analysis module is connected with the writing FIFO module, and the output of the writing FIFO module is connected with the receiving end FIFO; the output of the transmitting end FIFO is connected with the reading FIFO module, the output of the reading FIFO module is connected with the data packet transmitting module, and the output of the data packet transmitting module is connected with the 40G IP core. According to the invention, fewer FPGA resources can be occupied, and the requirements of high-speed data transmission and interaction between the upper computer and the FPGA are met.

Description

technical field [0001] The invention belongs to the technical field of high-speed transmission, and relates to a high-speed data transmission architecture and an implementation method of a host computer and an FPGA based on a UDP protocol. Background technique [0002] FPGA (Field Programmable Gate Array) is a semi-custom circuit. Due to its advantages of reconfiguration, high energy efficiency, high performance, portability, and low latency, it has an irreplaceable position in data centers, communications, artificial intelligence and other fields. . [0003] FPGA-based high-performance data processing boards are often equipped with high-speed optical fiber interfaces for data interaction with the host computer or other devices. The IP core (Intellectual Propertycore) for optical fiber communication provided by FPGA manufacturers mainly works at the physical layer or the data link layer, and does not support the upper-layer transmission protocol, while the existing network ...

AI Technical Summary

Problems solved by technology

The IP core (Intellectual Propertycore) for optical fiber communication provided by FPGA manufacturers mainly works on the physical layer or the data link layer, and does not support the upper-layer transmission protocol. However, the existing network transmission protocols based on FPGA are often redundant and occupy There are many resources and the transmission rate of tens of Gbs cannot be achieved

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