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Translation lookaside buffer (TLB) (mTLB) in process-specific memory for enhancing memory management unit (MMU) TLB for translating virtual addresses (VA) to physical addresses (PA) in processor-based systems

A memory management and central processing unit technology, applied in the field of memory management units, can solve problems such as large conversion overhead

Pending Publication Date: 2022-07-15
MICROSOFT TECH LICENSING LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Conversion overhead may be greater for customers running on nested hypervisors

Method used

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  • Translation lookaside buffer (TLB) (mTLB) in process-specific memory for enhancing memory management unit (MMU) TLB for translating virtual addresses (VA) to physical addresses (PA) in processor-based systems
  • Translation lookaside buffer (TLB) (mTLB) in process-specific memory for enhancing memory management unit (MMU) TLB for translating virtual addresses (VA) to physical addresses (PA) in processor-based systems
  • Translation lookaside buffer (TLB) (mTLB) in process-specific memory for enhancing memory management unit (MMU) TLB for translating virtual addresses (VA) to physical addresses (PA) in processor-based systems

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Embodiment Construction

[0026] Aspects disclosed herein include a process-specific in-memory translation lookaside buffer ( TLB) (mTLB). A processor-based system includes a processor having one or more central processing units (CPUs), each central processing unit (CPU) configured to execute computer software instructions for a process. The processor-based system also includes a memory system including main physical memory addressable by the PA. A processor is a virtual memory system that employs virtual addressing to make the memory space available memory greater than the amount of physical memory space in the main system memory of the processor-based system. In some examples, each CPU is provided with a shared or dedicated MMU for converting VA to PA. The MMU is associated with a system in-memory TLB ("MMU TLB") and page tables (which are memory circuits). System memory is memory that is fully addressable by the PA space of a processor-based system. The MMU TLB is the cache memory associated wit...

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Abstract

A process-specific memory translation lookaside buffer (TLB) (mTLB) for enhancing a memory management unit (MMU) TLB for translating a virtual address (VA) to a physical address (PA) in a processor-based system is disclosed. In disclosed examples, an in-store TLB that is specific for each process is supported in system memory such that a cache page table entry of one process does not replace a cache page table entry of another process. When a process is scheduled to execute in a central processing unit (CPU), an in-memory TLB address stored for the process may be used by a page table traversal circuit in the CPU MMU to access a dedicated in-memory TLB for executing a process for performing a VA to PA translation when a TLB miss occurs in the MMU TLB. If a TLB miss occurs in the in-store TLB, the page table traversal circuit may traverse the page table in the MMU.

Description

technical field [0001] The techniques of this disclosure relate to processor-based systems employing a central processing unit (CPU) (also referred to as a "processor"), and more particularly to being accessed to provide virtual address (VA) to physical address (PA) translation The memory management unit (MMU) in the processor includes the translation lookaside buffer (TLB) and page tables. Background technique [0002] Microprocessors, also known as "processors," perform computing tasks for a wide variety of applications. A traditional microprocessor includes one or more central processing units (CPUs), also known as processor cores. The processor is implemented in a processor-based system that includes a memory system that is accessed to retrieve computer instructions for execution by the processor to perform tasks. The storage system is also accessed to retrieve data for executing the computer instructions. The results of executed computer instructions may be stored as...

Claims

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Application Information

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IPC IPC(8): G06F12/1009
CPCG06F12/1009G06F12/1027G06F12/1036G06F2212/651G06F2212/681G06F2212/683
Inventor M·T·文卡塔拉曼T·P·施派尔
Owner MICROSOFT TECH LICENSING LLC
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