Hyperparallel comparison method and system

A technology of line data and table items, applied in information technology and biological engineering, biological sequence comparison in protein engineering, genetic engineering, image recognition, natural language fields, can solve the problems that do not meet biological comparison, natural language data and images Differences in data comparison requirements, etc.

Pending Publication Date: 2022-07-22
丁贤根
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0013] Although TCAM can achieve single-cycle comparison of tens of millions of data, its original design is for the routing table of the router, which is seriously different from the comparison requirements of biological data, natural language data, and image data, and does not meet the requirements of biological comparison. right request

Method used

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  • Hyperparallel comparison method and system
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  • Hyperparallel comparison method and system

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specific Embodiment 1

[0190] Specific embodiment 1: biological sequence hyperparallel alignment server

[0191] 1. Description of the module structure diagram

[0192] like Figure 5 It is an embodiment of the biological sequence hyperparallel alignment server of the present invention. In the figure, two comparison units are used, of which the comparison unit 1 is larger, the entry width is 256 bytes, the depth is 1M entry lines, and 1 million entry lines are compared at one time in a single cycle; the comparison unit 2 is smaller, the entry width is 64 bytes, the depth is 16, and 16 entry lines are compared at one time in a single cycle. If it is a SAM file for biological sequences, the alignment can be performed in units of bytes. In this case, such as figure 2 the logical definition of the byte-based alignment unit shown, and Figure 4 The alignment array of and Figure 5 It is also a logical definition of a byte-based comparison array; otherwise, it is a logical definition of a binary bit...

specific Embodiment 2

[0356] Specific embodiment 2: PCIE card overspeed comparison system

[0357] like Image 6 As shown, this embodiment is another application of the present invention—the PCIE card-type overspeed comparison system. The same as the previous embodiment will not be repeated here, and only the differences will be emphasized here.

[0358] 1. Use TCAM chip or FPGA to design PCIE card overspeed comparison system. The system includes: comparator array, management module, shift controller, reconfigurable logic, memory and table entry mapping and PCIE interface.

[0359] 2. The system needs to be inserted into the PCIE slot of the PC to run, and does not have the ability to run independently.

[0360] 3. The system includes a comparison unit, which adopts the built-in CPU and program design of the TCAM chip as the management module of the system.

[0361] 4. The management module of this system designs a management interface for the host PC.

[0362] 5. The entry width of this syste...

specific Embodiment 3

[0363] Specific embodiment three: general data overspeed comparison system

[0364] like Image 6 As shown, this embodiment is another application of the present invention - a general data overspeed comparison system. The same as the previous embodiment will not be repeated here, and only the differences will be emphasized here.

[0365] 1, Figure 4 The alignment array is defined using bit alignment based logic, such as figure 1 shown.

[0366] Therefore, for the step S109, the logic defines that the site adopts bits, and the alignment is based on a bit-by-bit alignment.

[0367]2. For the comparison of image data, the width of the table entry is suitable for the image size. For example, the 4K-based RGB three-primary color video image format, when each picture is 3840*2160 pixels, determine the width of the table entry to be 3840*3* 24bits=270Kbits, the entry depth is 2160*3*24bits=151875bits=152Kbits, and the entry depth can also be increased. Each entry can store mult...

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Abstract

An FPGA (Field Programmable Gate Array), a programmable logic or a TCAM (Ternary Content Addressable Memory) chip is adopted to design a single-cycle hyper-parallel comparison method, so that the simultaneous bit-by-bit comparison of a keyword item and a plurality of table item rows is completed in a single logic cycle, and matched table item row addresses, and statistical data and position information of different and same points are output. The algorithm supports table item reconfiguration, different and identical site processing, filter filtering, table item mapping, and comparison of a one-dimensional array, two-dimensional data and multi-dimensional data; the system comprises a comparator array, reconfigurable logic, a different and same site processor, a mapping memory, a filter and a communication interface. And an independent comparison server and a PCIE acceleration card can be formed. According to the method, when 10M table item rows are compared, the speed is increased by more than 109 orders of magnitude compared with the current fastest Von computer comparison algorithm of a CPU (Central Processing Unit).

Description

[0001] This application is a division of an invention application with application number 201910775554.1 filed on August 21, 2019. technical field [0002] The invention relates to the fields of information technology and biological engineering, in particular to the subfield of biological sequence alignment in genetic engineering and protein engineering, and the fields of natural language and image recognition. Background technique [0003] Biological sequence alignment, natural language processing and image alignment are emerging disciplines. The inventors have searched and researched and found that almost all of the existing alignment techniques are Fung's computer alignment algorithms, and some try to use GPU parallel algorithms. Its limitations are too large, and it cannot really achieve high-speed parallel comparison of specific data. [0004] TCAM (Ternary Content Addressable Memory, ternary content addressable memory), it uses bit comparison technology, so that after ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F16/903
CPCG06F16/90339G06F16/90344
Inventor 丁远彤丁贤根
Owner 丁贤根
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