37 results about "Processor mapping" patented technology

The invention discloses an MVC framework based on Spring and MyBatis, which belongs to the technical field of computer software. The front-end controller is DispatcherServlet; The mapper (Handler Mapping) performs processor management, and the view resolver (View Resolver) performs view management; the page controller / action / processor is the implementation of the Controller interface. The invention establishes a development platform based on mature ideas such as MVC, and develops a more concise Web layer.

The embodiments herein discloses a system and method for designing SoC by using a reinforcement learning processor. An SoC specification input is received and a plurality of domains and a plurality of subdomains is created using application specific instruction set to generate chip specific graph library. An interaction is initiated between the reinforcement learning agent and the reinforcement learning environ lent using the application specific instructions. Each of the SoC sub domains from the plurality of SoC sub domains is mapped to a combination of environment, rewards and actions by a second processor. Further, interaction of a plurality of agents is initiated with the reinforcement learning environment for a predefined number of times and further Q value, V value, R value, and A value is updated in the second memory module. Thereby, an optimal chip architecture for designing SoC is acquired using application-domain specific instruction set (ASI).

The invention relates to a debugging system and a debugging method of a multi-core processor. The debugging system includes a debugging host, a target processor, and a mapping and protocol conversion device. The debugging host includes a debugger, and the target processor includes a plurality of cores. The mapping and protocol conversion device is connected between the debugging host and the target processor, identifies a core architecture to which each of the cores belongs, and maps each of the cores respectively to at least one thread of at least one process according to the core architecture to which each of the cores belongs. Afterwards, the debugger executes a debugging procedure on the target processor according to the process and the thread corresponded to each of the cores.

A sensor including optics configured in accordance with a display that presents a GUI, the optics projecting the GUI above the display such that the GUI is visible in-air, a reflectance sensor including light emitters projecting light beams towards the projected GUI, light detectors detecting reflections of the beams by objects interacting with the projected GUI, and a lens maximizing detection of light at each detector for light entering the lens at a respective location along the lens at a specific angle θ, whereby for each emitter-detector pair, maximum detection of light projected by the emitter of the pair, reflected by an object and detected by the detector of the pair, corresponds to the object being at a specific 2D location in the projected GUI, and a processor mapping detections of light for emitter-detector pairs to their corresponding 2D locations, and translating the mapped locations to display coordinates.

A system, method, and computer program product for managing storage volumes. A processor creates a first point-in-time copy cascade, where the first point-in-time copy cascade comprises a source volume, a first snapshot point-in-time copy volume, and a second snapshot point-in-time copy volume; the first volume is a snapshot copy of the source volume and the second volume is a snapshot copy of the first volume; and the source volume, the first volume, and the second volume include a host portion. A processor creates a third snapshot point-in-time copy volume from the first volume. A processor maps the third volume to create a second cascade, wherein the second cascade comprises the source volume, the first volume, and the third volume but not the second volume. A processor directs an I / O operation for the first copy volume to the third volume.

The present disclosure relates to a system and method for remotely operating one or more peripheral devices of a wireless device using a server and client architecture. In one aspect, the system may comprise a wireless device that includes a processor, a memory, a peripheral device, and a server adapted to communicate with the peripheral device; and a removable media device that includes a memory, a processor, and a client adapted to communicate with the server of the wireless device. In another aspect, the method may comprise the steps of emulating a hardware interface on a removable media device; mapping a peripheral device of a wireless device to the interface; mapping a processor of the media device to the peripheral device; wrapping and sending hardware commands from a client of the media device to a server of the wireless device; and executing the commands on the peripheral device.

The embodiments herein discloses a system and method for designing SoC by using a reinforcement learning processor. An SoC specification input is received and a plurality of domains and a plurality of subdomains is created using application specific instruction set to generate chip specific graph library. An interaction is initiated between the reinforcement learning agent and the reinforcement learning environment using the application specific instructions. Each of the SoC sub domains from the plurality of SoC sub domains is mapped to a combination of environment, rewards and actions by a second processor. Further, interaction of a plurality of agents is initiated with the reinforcement learning environment for a predefined number of times and further Q value, V value, R value, and A value is updated in the second memory module. Thereby, an optimal chip architecture for designing SoC is acquired using application-domain specific instruction set (ASI).

The invention belongs to the technical field of heterogeneous multi-processor computing, and particularly relates to a heterogeneous platform task scheduling method and system based on Q learning, which take all tasks as a Q learning state space, take a processor set as an action space, and wait for an allocated task as a current state. The method comprises the following steps: obtaining a task initial mapping scheme according to execution time required for mapping a task to an action space in Q learning; creating a genetic algorithm model, carrying out fitness evaluation on the task initial mapping scheme, setting individuals copied to the next generation of population in the genetic algorithm model according to fitness, carrying out crossover variation on reserved individuals, and determining new population optimization efficiency and a minimum threshold value; obtaining an approximately optimal solution mapped from a task to a processor in the model according to the genetic algorithm model; converting the model approximate optimal solution into ant colony information initial information distribution, and iteratively searching and outputting an optimal path through an ant colonyalgorithm according to the information distribution to obtain a task scheduling optimal scheme, so as to better improve the performance of the heterogeneous platform.

Memory management methods and computing apparatus with memory management capabilities are disclosed. One exemplary method includes mapping an address from an address space of a physically-mapped device to a first address of a common address space so as to create a first common mapping instance, and encapsulating an existing processor mapping that maps an address from an address space of a processor to a second address of the common address space to create a second common mapping instance. In addition, a third common mapping instance between an address from an address space of a memory-management-unit (MMU) device and a third address of the common address space is created, wherein the first, second, and third addresses of the common address space may be the same address or different addresses, and the first, second, and third common mapping instances may be manipulated using the same function calls.

One embodiment of the present invention provides a system for dynamically assigning vertices to processors to generate a recommendation for a customer. During operation, the system receives graph data with customer and product vertices and purchase edges. The system traverses the graph from a customer vertex to a set of product vertices. The system divides the set of product vertices among a set of processors. Subsequently, the system determines a set of product frontier vertices for each processor. The system traverses the graph from the set of product frontier vertices to a set of customer vertices. The system divides the set of customer vertices among a set of processors. Then, the system determines a set of customer frontier vertices for each processor. The system traverses the graph from the set of customer frontier vertices to a set of recommendable product vertices. The system generates one or more product recommendations for the customer.

The present invention relates to a method and system for mapping environments containing dynamic obstacles. In one embodiment, the present invention is a method for mapping an environment containing dynamic obstacles using a processor including the steps of forming a current instantaneous map of the environment, determining cells which are free space within the current instantaneous map, determining cells which are occupied space within the current instantaneous map, and integrating the current instantaneous map with an old integrated map of the environment to form a new integrated map of the environment.

The invention discloses a robot cluster scheduling system, comprising: a user layer, an intermediate layer, an application layer, a plug-in layer and a data persistence layer, the intermediate layer includes a processor mapping module and a state acquisition module, and the application layer includes a task scheduling module and a traffic Scheduling module, the plug-in layer includes task solving engine and traffic planning engine. The task solving engine is used to determine the target robot according to the parameters and state data of the task. The traffic planning engine is used to determine the target route. Both the task solving engine and the traffic planning engine provide APIs. On the one hand, it implements a robot cluster scheduling system that supports secondary development, and the system coupling is low. On the other hand, it realizes the determination of the target robot according to the task, realizes the optimal allocation of robot tasks, and improves the execution of tasks after scheduling. Efficiency, on the other hand, can intelligently plan the traffic route of the robot to prevent traffic jams of the robot.

The present invention relates to a method and system for mapping environments containing dynamic obstacles. In one embodiment, the present invention is a method for mapping an environment containing dynamic obstacles using a processor including the steps of forming a current instantaneous map of the environment, determining cells which are free space within the current instantaneous map, determining cells which are occupied space within the current instantaneous map, and integrating the current instantaneous map with an old integrated map of the environment to form a new integrated map of the environment.

The invention discloses a customer evaluation method and system based on big data. The method comprises the steps of obtaining first evaluation request information of a first evaluation page; sending the first evaluation request information to a front-end controller to obtain first to-be-processed request information; obtaining a first return processor from the processor mapper sent by the front-end controller; sending a first execution instruction to a processor adapter through the front-end controller, and inputting first evaluation data information into a customer satisfaction evaluation model; obtaining first return data information according to the customer satisfaction evaluation model; according to the front-end controller, analyzing the first return data information through the view analysis module, and obtaining first view display information; and sending the first view display information as first response data to the first user. Thus, the technical problem of low evaluation efficiency caused by too much customer evaluation data of logistics service in the prior art is solved.

The invention discloses techniques for dynamically compressing memory regions having a uniform value. Accesses between a processor and its external memory is reduced when the processor internally maintains a compressed version of values stored in the external memory. The processor can then refer to the compressed version rather than access the external memory. One compression technique involves maintaining a dictionary on the processor mapping portions of a memory to values. When all of the values of a portion of memory are uniform (e.g., the same), the value is stored in the dictionary for that portion of memory. Thereafter, when the processor needs to access that portion of memory, the value is retrieved from the dictionary rather than from external memory. Techniques are disclosed herein to extend, for example, the capabilities of such dictionary-based compression so that the amount of accesses between the processor and its external memory are further reduced.

Methods and systems are provided for assessing a target proximate a vehicle. A location and a velocity of the target are obtained. The location and the velocity of the target are mapped onto a polar coordinate system via a processor. A likelihood that the vehicle and the target will collide is determined using the mapping.