5 results about "Processor mapping" patented technology

The invention relates to the technical field of database management, and provides a multi-compatible database grammar intelligent processing method, which comprises the following steps of: receiving an SQL (Structured Query Language) statement sent by a client through a central grammar, performing grammar feature analysis on the received SQL statement, and identifying a target database grammar type to which the SQL statement belongs; the central syntax device queries a preset syntax type-processor mapping relation according to the recognized target database syntax type, and distributes an SQL statement route to a sub-syntax device corresponding to the target database syntax type; the sub-syntax device analyzes the received SQL statement and converts the SQL statement into a standard abstract syntax tree conforming to the internal specification of a database kernel; an execution plan is generated based on the standard abstract syntax tree, the plan being executed by an execution engine of the database kernel to return a result. According to the method, kernel-level native compatibility can be realized, and the comprehensive cost of database migration and fusion is remarkably reduced.

This application relates to a method, apparatus, and storage medium for handling defects in vehicle-mounted modules. The method includes: acquiring defect description information of an integrated vehicle system; the integrated vehicle system includes multiple vehicle-mounted modules; using a large model to perform location analysis on the defect description information to obtain the vehicle-mounted module category to which the defect description information belongs; the vehicle-mounted module category is the category of the vehicle-mounted module to which the defect described in the defect description information points, obtained by the large model based on business logic knowledge in the vehicle domain; based on the vehicle-mounted module category and a preset module-processor mapping relationship, assigning the defect task corresponding to the defect description information to a target processor; the module-processor mapping relationship includes the correspondence between vehicle-mounted modules and processors. This application solves the problem of low efficiency in handling defects in vehicle-mounted modules.

In a multi-processor computing device having a Universal Flash Storage (UFS) host controller interface operating in Multi-Circular Queue (MCQ) mode, mappings between processors and completion queues (CQs) may be dynamically changed based on one or more conditions. A condition may be detected that may impair the performance of one of the processors in accessing a CQ. When such a condition is detected, the UFS host controller system may update a queue-to-processor mapping, which may include replacing an association between a CQ and a processor with an association between the CQ and another processor.

Mapping instructions included in threads to functional units of processors is disclosed. A first functional unit of a first processor may be identified that is underutilized for a first instruction included in a first thread of threads generated from a loop within source code. The first thread may be yielded to a second thread of the threads generated from the loop. A second instruction included in the second thread may be mapped to the first functional unit of the first processor.

The method of single cycle super parallel comparison is designed by using FPGA, programmable logic or TCAM chip, which can complete the bitwise comparison between the key item and multiple table rows in a single logic cycle, output the address of the matched table row, and output the statistics data and position information of the same and different points. The algorithm supports table reconfiguration, same and different point processing, filter filtering, table mapping, one-dimensional array, two-dimensional data and multi-dimensional data comparison; the system includes a comparator array, reconfigurable logic, same and different point processor, mapping memory, filter, communication interface. It can form an independent comparison server and PCIE acceleration card. The method can speed up more than 10 9 orders of magnitude compared with the fastest CPU von Neumann computer comparison algorithm when comparing 10M table rows.