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Page buffer, programming method, memory device and system

A page buffer and memory technology, applied in static memory, read-only memory, digital memory information, etc., can solve the problems of non-volatile storage device performance deterioration and narrowing of read margin, etc., to improve stability and performance. The effect of read and write accuracy, wide read margin, and narrow threshold voltage distribution

Pending Publication Date: 2022-07-22
YANGTZE MEMORY TECH CO LTD
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In the case where the threshold voltage distribution is wide, the read margin becomes narrow, thereby deteriorating the performance of the nonvolatile memory device

Method used

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  • Page buffer, programming method, memory device and system
  • Page buffer, programming method, memory device and system
  • Page buffer, programming method, memory device and system

Examples

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Embodiment Construction

[0088] In order to facilitate understanding of the present invention, the present invention will be described more fully hereinafter with reference to the related drawings. Preferred embodiments of the invention are shown in the accompanying drawings. However, the present invention may be embodied in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0089] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terms used herein in the description of the present invention are for the purpose of describing specific embodiments only, and are not intended to limit the present invention. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0090] like Figure 1A...

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Abstract

The embodiment of the invention discloses a page buffer, a programming method, a memory device and a system, the page buffer is arranged corresponding to a bit line of a memory cell array of the memory device, and the page buffer comprises a first charging and discharging module, a second charging and discharging module and a memory cell array, the memory is configured to store first bit line forcing information and provide a first bit line forcing voltage to the bit line according to the first bit line forcing information; the second charging and discharging module is coupled with the bit line and is configured to be capable of storing second bit line forcing information and providing a second bit line forcing voltage different from the first bit line forcing voltage to the bit line according to the second bit line forcing information; wherein the first bit line forced voltage and the second bit line forced voltage are both larger than a normal programming bit line voltage and smaller than a forbidden programming bit line voltage.

Description

technical field [0001] Embodiments of the present disclosure relate to semiconductor technology, and relate to, but are not limited to, a page buffer, a programming method, a memory device, and a system. Background technique [0002] Non-volatile memory cells, such as NAND flash memory cells, are capable of program / erase operations and are performed by varying threshold voltages when electrons are migrated by means of a strong electric field applied to a thin oxide layer remove operation. [0003] When a programming operation is performed on a nonvolatile memory device, the threshold voltages of the plurality of memory cells may be programmed to different values, eg, the threshold voltages are distributed with a certain degree of variation. In the case where the threshold voltage distribution is wide, the read margin becomes narrow, thereby deteriorating the performance of the nonvolatile memory device. In particular, where there are three or more threshold distributions c...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C16/10G11C7/12
CPCG11C16/10G11C7/12G11C16/24G11C16/30G11C16/32G11C7/106G11C7/1087
Inventor 杜智超王砚宋大植王瑜
Owner YANGTZE MEMORY TECH CO LTD
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