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Wafer arrangement method of topological structure laser chip

A topology and chip technology, used in lasers, laser parts, semiconductor lasers, etc., to reduce costs

Active Publication Date: 2022-07-22
SHENZHEN AFALIGHT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] like Figure 2 to Figure 4 As shown, as mentioned above, the main disadvantages of the prior art are summarized as follows. In order to cooperate with the multi-channel transmission of traditional optical communication, the standard pitch of the channel interval in the central active area of ​​the VCSEL chip is equal to 250 microns, which is limited by the single topology VCSEL chip. Due to the limitation of wafer layout, the distance between every two adjacent chip units 9 must also be kept at 250 microns, so in a multi-channel optical fiber system, the cost of the laser array required for a single product needs to be lower (more chip units 9 are arranged on the same wafer), the above-mentioned wafer arrangement method can no longer meet the production requirements, and this is the main shortcoming of the prior art

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  • Wafer arrangement method of topological structure laser chip
  • Wafer arrangement method of topological structure laser chip
  • Wafer arrangement method of topological structure laser chip

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Experimental program
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Embodiment Construction

[0041] like Figure 5 to Figure 12 As shown, a method for arranging a topological structure laser chip on a wafer includes the following steps.

[0042] like Figure 5 As shown, the first step is to arrange the chip boundary array on the wafer.

[0043] The chip boundary array includes a plurality of boundary units 10 , and a plurality of the boundary units 10 are arranged on the wafer to form the chip boundary array.

[0044] like Image 6 As shown, each of the boundary units 10 includes a horizontal side and a vertical side, the length of the horizontal side is L, and the length of the vertical side is W.

[0045] The horizontal side includes a top side 11 and a bottom side 12 , the vertical side includes a left side 13 and a right side 14 , and a unit surface 15 is formed by the top side 11 , the bottom side 12 , the left side 13 and the right side 14 .

[0046] like Figure 7 to Figure 9 As shown, in the second step, in the first step, the first topology structure 100 a...

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Abstract

The invention relates to a wafer arrangement method for topological structure laser chips, which comprises the following steps of: 1, arranging a chip boundary array on a wafer, the chip boundary array comprising a plurality of boundary units, and 2, arranging a first topological structure and a second topological structure on the unit surface of each boundary unit in the first step, wherein the first topological structure comprises a first active area, a first electrode bonding pad and a first wire, and the second topological structure comprises a second active area, a second electrode bonding pad and a second wire.

Description

technical field [0001] The invention relates to a method for arranging laser chips, in particular to a method for arranging laser chips on a wafer for production. Background technique [0002] In the field of optical communication, the cost of vertical cavity surface emitter lasers (VCSELs) used in optoelectronic modules is calculated according to the number of VCSEL chips that can be produced by an average wafer. The more the number of chips, the lower the manufacturing price of a single VCSEL chip, so the smaller the area of ​​a single VCSEL chip, the more VCSEL chips each wafer can produce, and the lower the cost of a single VCSEL chip, Then in traditional multi-channel optical communication systems, the cost of VCSEL chips required for each product is lower. [0003] like figure 1 As shown, in the traditional multi-channel optical fiber system, the VCSEL chips adopted in the prior art solution are all of single topology structure. The VCSEL chip includes a substrate 1...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01S5/02H01S5/183H04B10/25H04B10/50
CPCH01S5/02H01S5/021H01S5/0201H01S5/183H04B10/503H04B10/25
Inventor 黄君彬付全飞童小琴杨勇陈纪辉
Owner SHENZHEN AFALIGHT CO LTD