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Multiply-add operation device and multiply-add operation control method thereof

A control method and technology of addition operation, applied in the direction of calculation, energy-saving calculation, and calculation using the number system to achieve the effect of improving calculation efficiency and reducing power

Pending Publication Date: 2022-07-29
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, under the premise that the amount of data to be processed is increasing, how to reduce the power consumption required by the arithmetic unit in the memory has become an important issue

Method used

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  • Multiply-add operation device and multiply-add operation control method thereof
  • Multiply-add operation device and multiply-add operation control method thereof
  • Multiply-add operation device and multiply-add operation control method thereof

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Embodiment Construction

[0059] Please refer to figure 1 , figure 1 A schematic diagram of a multiply-add device according to an embodiment of the present invention is shown. The multiply-add operation device 100 includes a feature information filter 110 and an in-memory operator 120 . The characteristic information filter 110 records a plurality of designated bits of a plurality of characteristic information. The characteristic information filter 110 receives the set bit DIN1 of the input information, and is used for comparing the set bit DIN1 of the received input information with the designated bit of the stored characteristic information to generate a comparison result, and to generate a filter according to the comparison result address SADD.

[0060] In detail, the above-mentioned characteristic information can be extracted from a sample information. In the artificial intelligence system, taking the application of image recognition as an example, the designer can establish sample information ...

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Abstract

The invention discloses a multiply-add operation device and a control method thereof. The multiply-add operation device comprises a feature information filter and an arithmetic unit in a memory. The feature information filter records a plurality of designated bits of a plurality of pieces of feature information, compares the received input information with the designated bits to generate a comparison result, and generates a screening address according to the comparison result. An arithmetic unit in the memory records all bits of the feature information. The arithmetic unit in the memory multiplies and adds the feature information and the input information according to the screening address to generate an operation result.

Description

technical field [0001] The present invention relates to a multiply-add operation device and a control method for the multiply-add operation, and more particularly, to a multiply-add operation device and a control method for the multiply-add operation that can reduce power consumption. Background technique [0002] With the advancement of electronic technology, artificial intelligence has also flourished. In order to provide more efficient artificial intelligence computing tools, so-called in-memory operators have been proposed. [0003] In addition, in the technical field of image comparison, content addressable memory plays an important role. In the known art, static memory is commonly used to implement content addressable memory. However, in today's technical field, static memory cannot provide the high density required by circuits. [0004] An in-memory operator built from non-volatile memory is also a viable approach. However, under the premise that the amount of dat...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/544G11C8/14G11C16/08
CPCG06F7/5443G11C8/14G11C16/08G06F2207/4824Y02D10/00G06F7/523G06F2207/4826G06F7/02G06F7/50
Inventor 曾柏皓李峯旻林榆瑄
Owner MACRONIX INT CO LTD