Split-gate flash memory unit and preparation method thereof
A storage unit and flash technology, applied in electrical components, semiconductor devices, circuits, etc., can solve the problems of large unit area and high read voltage
Pending Publication Date: 2022-07-29
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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Problems solved by technology
[0003] The object of the present invention is to provide a split-gate flash memory unit and a preparation method thereof, so as to solve the problem that the existing split-gate flash memory unit has a larger unit area and a higher reading voltage
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preparation example Construction
[0070] figure 1 A flowchart of a method for preparing a split-gate flash memory cell provided in this embodiment is as follows: figure 1 As shown, the present invention provides a method for preparing a split-gate flash memory cell, comprising:
[0071] Step S1: providing a substrate on which a source line and two storage bits are formed, the two storage bits are symmetrically arranged, and the source line is located between the two storage bits;
[0072] Step S2: Each of the storage bits includes a floating gate, a gate dielectric layer, an erase gate, a word line gate and a tunnel oxide layer, and the floating gate, the gate dielectric layer, and the erase gate are sequentially stacked on the On the substrate, the gate dielectric layer includes a first dielectric layer and a second dielectric layer, the erase gate includes a first part and a second part, the first dielectric layer covers the floating gate, the second A dielectric layer covers part of the first dielectric l...
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The invention provides a split-gate flash memory unit and a preparation method thereof, the split-gate flash memory unit comprises a substrate, and a source line and two memory bits formed on the substrate, the two memory bits are symmetrically arranged, and the source line is located between the two memory bits; each storage bit comprises a floating gate, a gate dielectric layer, an erase gate, a word line gate and a tunneling oxide layer, the erase gate comprises a first part and a second part, and the first part extends along the horizontal direction. The second part extends along the vertical direction; the word line gate and the tunneling oxide layer are sequentially stacked on the substrate, and the word line gate extends upwards to cover the gate dielectric layer and the side wall of one side, far away from the source line, of the first part. According to the split-gate flash memory unit, the erase gate is divided into two parts, the size of a device is effectively reduced, meanwhile, the threshold voltage of the split-gate flash memory unit can be reduced through the arrangement of the erase gate, and reading operation under the low-voltage condition is achieved.
Description
technical field [0001] The invention relates to the field of semiconductor manufacturing, in particular to a split-gate flash memory cell and a preparation method thereof. Background technique [0002] Flash memory has the advantages of high storage density, good reliability and portability. Therefore, flash memory has been widely used in mobile and communication devices such as mobile phones, notebooks and U disks since its inception. Flash memory generally includes two structures: a stack gate and a split gate structure. Currently, the split gate structure is widely used. With the continuous reduction of the size of semiconductor devices, the existing split gate structure Flash memory generally has the problems of large area and excessive source line resistance. SUMMARY OF THE INVENTION [0003] The purpose of the present invention is to provide a split-gate flash memory cell and a preparation method thereof, so as to solve the problems of large cell area and high read ...
Claims
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IPC IPC(8): H01L27/11521H01L27/11548H01L29/423H01L21/28H10B41/30H10B41/50
CPCH01L29/40114H01L29/42328H10B41/30H10B41/50
Inventor 李冰寒
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP