Multi-input LUT layout method based on FPGA

Abstract

The invention provides a multi-input LUT layout method based on an FPGA, which realizes that at least one external signal input port is added in a logic area LP of the FPGA and is used when a register in the LP accesses an external input signal. The FPGA is arranged, and when a register is driven by an external signal and wiring conflicts occur, input ports used by the LUT and the number of the input ports are judged. When the input port and the output port of the LUT are suspended, any one suspended input end and any one suspended output end of the LUT are arranged into a single-input single-output gating device through mode selection setting, the input end of the gating device is used for providing a new external input port for the register, and the output end of the gating device is used for providing a new external input port for the register. And logic functions realized by an input port and an output port which are originally used by the LUT are kept unchanged. According to the layout method, the number of LP units needing to be rearranged in the FPGA chip is reduced, the layout result of the FPGA chip is more compact, the wiring distance is shorter, and therefore electric signal transmission time delay is reduced.

Description

technical field [0001] The present application relates to the field of integrated circuit applications, and in particular, to a layout method of a multi-input LUT based on an FPGA. Background technique [0002] In the comprehensive implementation stage of the FPGA (Field Programmable Gate Array) chip design process, the comprehensive layout stage compiles the circuit designed by the hardware description language into a logic netlist connected by basic logic units. The basic components of the netlist are mainly: Various types of registers REG (Register) and multi-input lookup table LUT (Lookup table). Later in the implementation routing phase, the program assigns these netlists to gates that actually exist on the chip and determines their connection paths. [0003] Generally, an FPGA chip includes a plurality of Programmable Logic Blocks (PLBs). Based on different models, each PLB includes a certain number of logic areas LP (Logic Parcel), and each LP includes a certain numb...

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Problems solved by technology

[0003] Usually, the FPGA chip includes a plurality of programmable logic blocks (Programmable Logic Block, PLB), based on different models, each PLB includes a certain number of logic areas LP (Logic Parcel), each LP includes a certain number of look-up tables LUT, The register REG, the adder ADD and the multiplexer MUX, etc., in the layout stage, the PLB is used as an independent unit, and the signals to realize the logic mapping are not only from the inside of the PLB, but also from the input signal from the outside of the PLB, because each The resources for routing external input signals in LP are limited, and it is often necessary to find a new LP for layout, which will cause waste of main resources LUT, REG, etc. in the new LP

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