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Method for using hard mask for critical dimension growth containment

A critical dimension and hard mask technology, which is applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve the problem that the increase of critical dimension is not particularly beneficial

Inactive Publication Date: 2004-05-05
TEGAL CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, these soft and hard masks have been found not to be particularly beneficial for controlling the increase in CD

Method used

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  • Method for using hard mask for critical dimension growth containment
  • Method for using hard mask for critical dimension growth containment
  • Method for using hard mask for critical dimension growth containment

Examples

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Embodiment Construction

[0026] The method of the present invention may be carried out in a corrosion reactor such as the corrosion reactor shown in FIG. 4 . It should be understood that other reactors including, but not limited to, corrosion reactors may be used, and such other reactors are included within the spirit and scope of the present invention.

[0027] The corrosion reactor of Figure 4 is indicated by numeral 20 and is configured as a multi-frequency, three-electrode reactor. Etching apparatus 20 includes housing 22 and etching chamber 24 . Wafer 26 is positioned on a chuck mounted on lower electrode 28 . The chamber 24 also includes a side electrode 30 and an upper electrode 32 . In a preferred embodiment, the skirt electrode 30 may be grounded, or may be capable of establishing a floating potential, resulting in a plasma in the chamber 24 . The upper electrode 32 is generally grounded, but it can also be designed to have a floating potential. In typical operation, as shown in FIG. 4, t...

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Abstract

A method for containing the critical dimension growth of the feature on a semiconductor substrate includes placing a substrate with a hard mask comprised of a reactive metal or an oxidized reactive metal in a chamber and etching the wafer. The method further includes using a hard mask which has a low sputter yield and a low reactivity to the etch chemistry of the process.

Description

Contents of the invention [0001] The present invention relates to a method of minimizing and limiting the increase in critical dimensions of structures on semiconductor wafers and on any other product that can be formed using semiconductor processing techniques, such as magnetic heads for disk drives and flat panel displays. Background technique [0002] The critical dimension (CD) of a structure on a semiconductor wafer or any product utilizing semiconductor processing technology refers to the width of said structure. The pitch is generally defined as the critical dimension plus the distance to the next structure. [0003] In the case of semiconductor processing methods using etching techniques, a lithographic masking layer such as a photoresist layer may be formed on top of a material to be etched. The photoresist layer defines the desired structure, masks portions of the underlying layer that are not to be etched, and exposes portions that are to be etched. During the e...

Claims

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Application Information

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IPC IPC(8): H01L21/302H01L21/027H01L21/033H01L21/3065H01L21/308H01L21/3213
CPCH01L21/3081H01L21/32139H01L21/0332H01L21/027
Inventor 斯蒂芬·P·德奥尼拉斯莱斯利·G·杰德艾尔弗尔德·科弗
Owner TEGAL CORP