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Mfg. method for capacitor having semi-spherical srystal grains

A capacitor, hemispherical technology, applied in the field of manufacturing capacitors, can solve the problem of not being able to obtain

Inactive Publication Date: 2004-05-26
RENESAS ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, the HSG of the required size cannot be obtained

Method used

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  • Mfg. method for capacitor having semi-spherical srystal grains
  • Mfg. method for capacitor having semi-spherical srystal grains
  • Mfg. method for capacitor having semi-spherical srystal grains

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Embodiment Construction

[0018] Embodiments of the present invention will be described below with reference to the drawings.

[0019] refer to Figures 1(a) to 1(f) , selectively depositing a first element isolation film 3 and a gate oxide film on the surface of the p-type silicon substrate 1 to form a plurality of gate electrodes 4 which also function as word lines. In addition, a plurality of N-type diffusion layer regions 2 are formed. Next, an interlayer dielectric layer is formed on its entire surface, and then a bit line connected to the source region is formed. In addition, an interlayer dielectric layer is formed on its entire surface. Subsequently, a node contact hole reaching the drain region is formed, and N-type doped amorphous silicon connected to the diffusion layer region 2 is grown through the node contact hole. Then etch back treatment is performed to form capacitor contact plugs 6 . Thereafter, on the entire surface, 40 nm thick silicon nitride 7, 800 nm thick borophosphosilicate...

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PUM

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Abstract

The invention provides a method for producing a capacitor, the size of the HSG can be appropriately and uniformly controlled, and depletion in the HSG is prevented.A first amorphous silicon layer is formed to connect to a portion of a capacitor contact plug, and then a second amorphous silicon layer and a third amorphous silicon layer are formed thereon. The first and the third amorphous silicon layers are formed so that they have a lower impurity concentration than that in the second amorphous silicon layer. HSG (hemispherical grain) is grown on surfaces of the first and the third amorphous silicon layers, and subsequently an impurity is diffused from the second amorphous silicon layer to the HSG so as to form a lower electrode.

Description

technical field [0001] The present invention relates to a method of manufacturing a capacitor, and more particularly to a method of manufacturing a capacitor having hemispherical grains (HSG) formed on the surface of a lower electrode. Background technique [0002] From the era of 1MB DRAM to the present, a stacked capacitor having an amorphous silicon film as an electrode has been widely used as a DRAM cell. However, in the conventional structure, it is difficult to maintain a sufficient capacitance value while increasing the degree of integration by reducing the cell size. Thus, methods of effectively increasing the surface area (area opposite to the upper electrode) of the lower electrode have been studied, for example, a method of making the lower electrode cylindrical, or a method of forming HSG on the surface of the electrode. [0003] An example of a conventional method of making such a capacitor is shown in FIGS. 3 and 4 . [0004] An example of the fabrication met...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/04H01L21/02H01L21/822H01L21/8242H01L27/108
CPCH01L28/90H01L28/82H01L27/10855H01L28/84H10B12/0335H01L28/75H01L28/91
Inventor 藤原秀二广田俊幸
Owner RENESAS ELECTRONICS CORP