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Data flow processor

A technology of data flow and processing devices, applied in the direction of TV, color TV parts, electrical components, etc., can solve problems such as limited and impossible to fully consider

Inactive Publication Date: 2005-02-16
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, limited by time and space, it is impossible for designers at this stage to fully consider all future usage methods, so the future application range will be limited by the assumptions made by people when designing the system

Method used

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Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0027]

[0028] figure 1 It is a block diagram showing the overall configuration of the digital TV receiver system according to the first embodiment of the present invention. figure 1 The system shown includes: digital TV receiver 100, AVHDD112 and digital VTR113.

[0029] The digital TV receiver 100 includes: a data flow processor 101 , a memory 106 , a CPU 107 , an AV decoder 108 and a hard disk 109 .

[0030] The data stream processor 101 includes: tuners 110 and 111 , a matrix switch 102 , an IEEE1394 interface 103 , a demultiplexer 104 and an HDD interface 105 . The tuners 110 and 111 are tuners for receiving digital TV broadcast, and output the received broadcast data stream to the matrix switch 102 . The broadcast data stream from the digital TV tuners 110 and 111 , the data stream from the IEEE1394 bus B2 , and the TV broadcast data stream from the hard disk 109 are input into the data stream processor 101 . The input data stream is processed and ...

Embodiment 2

[0103]

[0104] Image 6 It is a block diagram showing the overall configuration of a digital TV receiver system according to Embodiment 2 of the present invention. Image 6 The system shown includes: digital TV receiver 500 , AVHDD 112 and digital camcorder 508 .

[0105] The digital TV receiver 500 includes: a data flow processor 501 , a memory 106 , a CPU 107 , an Ethernet (R) interface 507 , and a DVD drive 509 .

[0106] The data stream processor 501 includes: a tuner 111 , a matrix switch 502 , an IEEE1394 interface 503 , a demultiplexer 504 , an AV decoder 505 , an HDD interface 105 and a DMA circuit 506 . The broadcast data stream from the tuner 111 , the data stream from the bus B2 and the TV broadcast data stream from the DVD drive 509 are input to the data stream processor 501 . The input data stream is processed and either stored in the memory 106 or output as a processed data stream. In addition, there are cases where the input data stream is o...

Embodiment 3

[0159] Embodiments 1 and 2 describe the case where the switch group of the matrix switch selects one data stream from the eight input data streams and outputs it. The third embodiment is characterized in that the switch group of the matrix switch can output multiple data streams after multiplexing.

[0160]

[0161] Figure 9 It is a block diagram showing the configuration of the switch group according to the third embodiment of the present invention. Configuration other than the switch block and Image 6 and Figure 7 The system shown is the same. refer to Figure 9 , each data stream 0~7, the data enable signals 0~7 representing valid data input are fetched by the respective registers 800~807 when they become active. In addition, the data enable signals 0-7 are input to the multiplexing control circuit 808, and the multiplexing control circuit 808 manages information on which register among the registers 800-807 stores data. In addition, the multipl...

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PUM

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Abstract

The stream processor of the present invention includes: a selection section and first to fifth processing sections. In the selection section, a plurality of inputs are associated with a plurality of outputs according to control from outside so that streams sent to the plurality of inputs are passed to the associated outputs. The first processing section sends a first stream to the first input among the plurality of inputs. The second processing section sends a second stream to the second input among the plurality of inputs. The third processing section receives a stream from the first output among the plurality of outputs. The fourth processing section receives a stream from the second output among the plurality of outputs. The fifth processing section receives a stream from the third output among the plurality of outputs, subjects the received stream to predetermined processing, and sends the processed stream to the third input among the plurality of inputs.

Description

technical field [0001] The invention relates to a data stream processor for processing multiple data streams. technical background [0002] In recent years, more and more images, sounds and data are played, transmitted and stored through digital data. Such as digital TV playback, DVD, digital VTR, digital video recorder, IEEE1394, etc., all combine data such as image signals, sound signals, data playback signals, and EPG as data streams for playback, transmission, processing, and storage. The data formats of these data streams vary. For example, digital TV and digital VTR use the transmission data stream specified in the MPEG system standard; DVD uses the program data stream specified in the MPEG system standard; In DV format. Thus, the format of these data must be handled uniquely. [0003] In this situation, not only digital AV machines with one function, but also digital AV machines with multiple functions appear. For example, a digital TV receiver with an IEEE1394 i...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H04N5/765H04N5/775
CPCH04N5/765H04N5/775
Inventor 沟端孝彦
Owner PANASONIC CORP
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