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Timer based blockage avoidance mechanism in high speed wireless communication system

A wireless communication system and timer technology, applied in transmission systems, digital transmission systems, communication between multiple stations, etc., can solve problems such as upper-layer protocol errors and data blocks not being transmitted in sequence.

Inactive Publication Date: 2005-05-04
INNOVATIVE SONIC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In this case, the data blocks are actually delivered out of order to the upper layer and may cause upper layer protocol errors

Method used

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  • Timer based blockage avoidance mechanism in high speed wireless communication system
  • Timer based blockage avoidance mechanism in high speed wireless communication system
  • Timer based blockage avoidance mechanism in high speed wireless communication system

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Embodiment Construction

[0030] The present invention modifies the prior art timer-based blocking avoidance mechanism to eliminate its inherent disadvantages. Instead of using only timers at the receiver to monitor data blocks lost in the reordering buffer, the present invention utilizes multiple timers at the transmitter to monitor the delivery of data blocks. The transmitter activates a corresponding timer for each transmitted data block with a new TSN, and when the transmitter receives an acknowledgment from the receiver for the transmitted data block, stops the corresponding timer on the transmitter for the transmitted data block. Additionally, if the timer expires before the transmitter receives such a corresponding acknowledgment for each data block, the transmitter discards the corresponding data block from the slave retransmission buffer and will not retransmit. The timer durations in the transmitter are preferably configured to be the same or shorter than those used by the reordering buffer a...

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Abstract

The present invention uses a timer on the transmitter to track transmitted data blocks to improve the timer-based congestion avoidance mechanism in the prior art. Furthermore, the present invention uses a multi-timer mechanism to manage the reordering buffer at the receiver. The multi-timer mechanism provides the receiver with one timer per reorder buffer, or one timer per lost data block, or one timer per lost data block, but the interval between consecutive TSN lost data blocks cannot be exceeded. Share a timer. A multi-timer mechanism can effectively track missing data blocks and monitor reorder transfer progress for all reorder buffers.

Description

[0001] application by reference [0002] This application claims priority to US Provisional Patent Application No. 60 / 345,676, published January 3,2002. technical field [0003] The present invention relates to a timer-based method and device for avoiding blocking caused by in-sequence transmission of a reordering buffer on a receiver in high-speed downlink packet access of a wireless communication system. Background technique [0004] In a wireless communication system, the High Speed ​​Downlink Packet Access (HSDPA) process uses adaptive modulation, Hybrid ARQ (Automatic Repeat Request) and other techniques to achieve high Access to the network) and UE (User Equipment) to obtain high peak rates. This relies on a new transport channel, HS-DSCH (High Speed ​​Downlink Multiplexing Channel), to handle the data exchange for the HSDPA process. [0005] The new functionality of hybrid ARQ and HSDPA is included in a new entity at the MAC (Media Access Control) layer called MAC-h...

Claims

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Application Information

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IPC IPC(8): H04L1/16H04L1/18H04L12/56H04L13/08H04L29/06H04L29/08H04Q7/22
CPCH04L1/1812H04L1/1841H04L1/1848H04L1/1851H04L1/1883H04L47/28H04L69/28H04L47/10
Inventor 江孝祥
Owner INNOVATIVE SONIC