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Digital signal processor with a reconfigurable system hardware stack

A digital signal and reconstruction system technology, applied in the direction of electrical digital data processing, instruments, machine execution devices, etc., can solve problems such as unfavorable application programs and adjustments, and achieve the effect of saving costs

Inactive Publication Date: 2006-05-10
SHANGHAI JIAOTONG UNIV +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The size of the hardware stack of the original general design system is fixed, which is not conducive to adjusting the optimal cost performance according to the actual application program

Method used

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  • Digital signal processor with a reconfigurable system hardware stack
  • Digital signal processor with a reconfigurable system hardware stack
  • Digital signal processor with a reconfigurable system hardware stack

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Embodiment Construction

[0010] like figure 1 As shown, the digital signal processor core 5 has a program control unit 1 , an address generator unit 2 , an instruction decoding unit 3 , and a digital data processing unit 4 , and a digital data memory 6 is connected to the digital signal processor core 5 . The instruction decoding unit 3 translates the instruction code into the control signal representing the meaning of the instruction inside the digital signal processor core 5, and these described control signals are connected to the program control unit 1, and the program control unit 1 sends the address generation unit 2, the instruction translation The code unit 3 and the digital data processing unit 4 send out the control signals needed to control the work of these modules. The digital data processing unit receives the data from the digital data memory 6 and performs operations on it. The address generator unit 2 performs address calculation, and the result of the address calculation is connected...

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Abstract

A digital signal processor with a reconfigurable system hardware stack belongs to the technical field of digital signal processing. The operating registers of the system hardware stack include a system hardware stack pointer register, and the system hardware stack pointer register is connected to the system hardware stack through an address bus. In the digital signal processor of the present invention, by setting the port value, the program can run under the environment of different system hardware stacks with 16 entries, 32 entries, 48 ​​entries or 64 entries, and the user can start from the minimum system hardware stack size Try to run the program, from small to large, evaluate the execution efficiency of the application on the basis of different system hardware stack sizes, and then consider the cost of each system hardware stack to find the optimal price / performance ratio. In this way, such a system hardware stack size can be used in mass production of chips in the future, which is of great benefit to saving costs.

Description

technical field [0001] The invention relates to a digital signal processor, in particular to a digital signal processor with a reconfigurable system hardware stack, belonging to the technical field of digital signal processing. Background technique [0002] "Digital Signal Processor Integrated Circuits (DSP Integrated Circuits)" (author: Lars Wanhammar) published by American Academic Press (Academic Press) in 1999 discloses a stack operation method of a digital signal processor in the prior art. In the existing digital signal processing operation process, for loop operations, subroutines and interrupt service routines, stack push and pop operations are required. In order to improve the operating efficiency of the program, different from the general CPU, the existing digital signal processor (DSP) generally adopts zero-overhead hardware loop, zero-overhead subroutine operation and interrupt service routine operation. The so-called zero overhead means that there is no need to...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/38G06F9/30
Inventor 陈进
Owner SHANGHAI JIAOTONG UNIV
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