Electric level transfer circuit
A level conversion and circuit technology, applied in the direction of circuit, logic circuit connection/interface layout, electrical components, etc., can solve problems such as duty cycle changes
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no. 1 Embodiment
[0027] Such as figure 2 As shown, the level conversion circuit of the first embodiment of the present invention has a first transfer circuit 1 that detects a rising edge of an input signal to form a rising edge signal and a second transfer circuit that detects a falling edge signal of an input signal to form a falling edge signal 2. And the output synthesis circuit 3 that synthesizes the rising edge signal and the falling edge signal. The first transfer circuit 1 has a signal input terminal 50 connected to a gate terminal, a first high voltage VCC1 is connected to a drain terminal, a low power supply VSS is connected to a back gate terminal, and an output synthesis circuit 3 The 1nth MOS transistor connected to the source terminal on the input terminal side. The second transmission circuit 2 has a first inverter 11 that connects the signal input terminal 50 to the input terminal, connects the first high-level power source VCC1 to the high-level power input terminal, and connects ...
no. 2 Embodiment
[0043] Such as Figure 4 As shown, the first transfer circuit 1 of the level conversion circuit of the second embodiment of the present invention uses the p MOS transistor P1, while the first embodiment uses the first n MOS transistor N1. This point is different. The first transfer circuit 1 has: a first pMOS transistor P1 that connects the output terminal of the first inverter I1 to the gate terminal, and connects the first high-level power source VCC1 to the source; and the first pMOS transistor P1 The second p MOS transistor is diode-connected between the drain terminal of the output and the first input terminal side of the output synthesis circuit 3. The second p MOS transistor P2 connects the drain terminal and the source terminal of the first p MOS transistor P1, and connects the first input terminal side of the output synthesis circuit 3 to the drain terminal and the gate terminal, respectively. Others are substantially the same as the first embodiment, so the repetitive des...
no. 3 Embodiment
[0047] Such as Figure 5 As shown, the difference between the first transfer circuit of the level conversion circuit of the third embodiment of the present invention is that the first p MOS transistor P1 described in the second embodiment is replaced with a side of the low-potential power supply VCC. The first p MOS transistor P31. The first transfer circuit 1 has a first p MOS transistor 31 having a backside gate terminal to which a first high-level power supply voltage is applied, a drain terminal to which a low power supply voltage Vg is applied, and a first input terminal side of the output combining circuit 3 The connected source terminal. The back gate terminal of the first p MOS transistor P31 is connected to the first high-level power supply VCC1. Others are substantially the same as the first embodiment, so repetitive descriptions are omitted.
[0048] If the level conversion circuit of the third embodiment is used, it is possible to reduce the delay of the rising edge of...
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