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Digital signal processor with a reconfigurable cache

A high-speed cache and digital signal technology, applied in the direction of electrical digital data processing, memory systems, instruments, etc., can solve the problems of low efficiency of multimedia applications, large data access, waste of area, etc.

Inactive Publication Date: 2006-08-02
上海领微科技有限公司 +1
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, many workloads use the cache inefficiently, resulting in a waste of area
For example, large caches are very effective for many general workloads, but are inefficient for multimedia applications due to the streaming nature of data access and the relatively large working sets in these applications

Method used

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  • Digital signal processor with a reconfigurable cache
  • Digital signal processor with a reconfigurable cache
  • Digital signal processor with a reconfigurable cache

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Embodiment Construction

[0010] figure 1 It is a block diagram of the digital signal processor involved in the present invention, which mainly describes the connection relationship of each component module of the overall digital signal processor. Such as figure 1 As shown, the digital signal processor has a program control unit 1, an address generator unit 2, an instruction decoding unit 3, and a digital data processing unit 4, a digital data memory 6, and an off-chip digital data memory 7; the first four units form a digital Signal Processor Core 5.

[0011] Such as figure 1 As shown, the instruction decoding unit 3 is connected to the program control unit. The program control unit 1 is connected to an address generation unit, an instruction decoding unit 3 and a digital data processing unit 4 . The digital data processing unit 4 is bidirectionally connected to an on-chip digital data memory 6 . The address generator unit 2 has an address bus connected to the on-chip digital data memory 6, and t...

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PUM

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Abstract

A digital signal processor with reconfiguration high speed buffer, wherein a specific high speed buffer reconfiguration register is arranged to determine the high speed buffer capacity needed, the high speed buffer address generator screens the corresponding high speed buffer address byte according to the information of the high speed buffer reconfiguration register. The digital signal processor according to the invention can make the program operate under the high speed buffer environment of 16K, 8K and 4K.

Description

technical field [0001] The invention relates to a digital signal processor, in particular to a digital signal processor with a reconfigurable high-speed cache, which innovates the utilization of the internal cache of a digital signal processor (DSP), and belongs to the technical field of computer digital signal processing. Background technique [0002] Title: DSP Integrated Circuits, Author: Lars Wanhammar, Publication Date: 1999, Publisher: Academic Press, A division of Harcourt Brace&Company 525BStreet, Suite 1900, San Diego, CA 92101-4495, USA [0003] Since Intel released its first 1K-bit DRAM in 1970, the size of DRAM has increased by more than 200,000 times, but its speed has increased by less than 20 times; more than 1,000 times. Especially in the past ten years, the speed of the processor has increased by more than 40% per year, and the speed of the main memory has only increased by about 11% per year. Therefore, the speed difference between the processor and the ma...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/00G06F13/14G06F9/30
Inventor 陈进
Owner 上海领微科技有限公司