Phase frequency detection device and method for reducing influence of mutation interference

Abstract

The detection device utilized in a phase locked loop compares target clock signal generated from feed back of the phase locked loop with an intended signal of reference clock as well as outputs a group of control signal. The said group of control signal is utilized to control the target clock signal to be synchronized with the intended signal of reference clock in following steps. The regulating system includes a reset module and a switching module. The reset module calculates the group of control signal, and if reset condition is accordant, the reset module outputs a group of reset signal. The switching module calculates the reset signal, and if switching condition is accordant, the switching module makes switching between normal operation mode and abrupt transition protection mode. When the detection device is in abrupt transition protection mode and the reset condition is accordant, the reset module outputs reset signal and resets the phase frequency detection device.

Description

technical field [0001] The present invention relates to an adjustment system of a phase-frequency detection device, in particular to a phase-frequency detection device and method that can reduce the impact of abrupt interference. Background technique [0002] see figure 1 , figure 1 It is a schematic diagram of a phase-frequency detection device 12 having a pair of flip-flops applied to a phase-locked loop 10 . A known phase-locked loop 10 includes a phase-frequency detection device 12 , a charge-discharge pump 40 , a voltage-controlled oscillator 42 and a frequency divider 44 . A known phase frequency detection device 12 with a pair of flip-flops is often applied to the phase locked loop 10 . The phase frequency detection device 12 is used to compare a target clock signal 20 generated by feedback from the phase-locked loop 10 with a predetermined reference clock signal 22, and output a set of control signals 26, 28, and subsequently control the target clock Signal 20 is...

AI Technical Summary

Problems solved by technology

Therefore, due to the sudden change 16, the phase frequency detection device 12 is often mistaken for a sudden change in the phase difference between the target clock signal 20 and the reference clock signal 22, and outputs a group of control signals 26, 28 affected by the sudden change 16. 26, 28 and then through the above-mentioned path, another corresponding feedback target clock signal 20 is produced, which greatly interferes with the original work

[0005] The time, place, cause and mechanism of mutation 16 cannot be fully predicted and prevented

In addition, the known phase-locked loop 10 only uses the phase frequency detection device 12 and the feedback control circuit 18 to control the target clock signal 20 so that it is synchronized with the reference clock signal 22

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