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Circuit and method for implementing correction operation to only read memory in inlaid program

A technology of read-only memory and memory, which is applied in the direction of read-only memory, memory system, static memory, etc., and can solve the problem that it cannot be changed anymore

Inactive Publication Date: 2007-01-24
INTEL CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The program memory can be implemented by dynamic random access memory, read-only memory, or a combination of dynamic random access memory and read-only memory; the program data stored in the read-only memory cannot be changed after the initial programming

Method used

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  • Circuit and method for implementing correction operation to only read memory in inlaid program
  • Circuit and method for implementing correction operation to only read memory in inlaid program
  • Circuit and method for implementing correction operation to only read memory in inlaid program

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Embodiment Construction

[0015] The present invention can be implemented to provide a correction mechanism embedded in a program (eg, ROM). The implementation of the present invention can effectively utilize the number of logic gates, and provide users with flexibility in use; the implementation of the present invention can be optimized for a specific digital signal processing core (such as: TeakLite digital signal processing core), or can Implemented in other digital signal processing cores, processors, or subsystems to meet implementation-specific design requirements. The timing of the present invention can also be adjusted to meet the requirements of a specific digital signal processing core, and the present invention can also be implemented in a modification mechanism of a digital signal processing subsystem, or in other forms of core circuits or modules as program memory, and the The core circuit or module cannot be changed arbitrarily.

[0016] Generally speaking, the processor accesses the pro...

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Abstract

Circuit and method for implementing correction operation to read-only memory in inlaid program. The present invention concerns an apparatus comprising a memory, a logic circuit and multiplexer. The memory generally comprises a first address space configured as read only and a second address space configured as read and write. The memory returns a first data item in response to a first address within the first address space. The logic circuit may be configured to (i) deassert a command signal in response to the first address not matching any of a plurality of predetermined addresses and (ii) generate a first branch instruction and assert the command signal in response to the matching. The multiplexer may be configured to select the first data item from the memory or the first branch instruction from the logic circuit in response to the command signal.

Description

technical field [0001] The present invention relates to embedded programs, and more particularly to circuits and methods for implementing patch mechanisms in embedded programs ROM. Background technique [0002] A conventional digital signal processing core is used to execute instructions read from a program memory. The program memory can be implemented by dynamic random access memory, read-only memory or a combination of dynamic random access memory and read-only memory; the program data stored in the read-only memory cannot be changed after initial programming. [0003] Modifying the logic allows programmers to have the opportunity to modify part of the program code in the ROM and replace part of the program code with different instructions to correct errors or improve a certain feature. Correction logic is typically used to redirect the normal flow of program code to a correction code. [0004] The traditional method (such as: U.S. Patent No. 4,610,000) will implement a ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F12/06G06F11/00G11C17/00G06F9/445G11C7/00G11C16/04G11C16/10G11C17/10G11C29/00
CPCG11C17/10G06F12/0638G06F8/66G06F9/30181
Inventor 阿朗·沙多
Owner INTEL CORP