Frame synchronized parallel scrambler and parallel de-scrambler

Abstract

Frame simultaneous parallel scrambler and parallel de-scrambler in transmission system of SDH are contained in timing clock simultaneous generated and parallel feedback shift register of 16 bits pseudo random sequence respectively. The feedback shift register is composed of shift register including 16 pieces of D trigger, and feedback network composed of 16 pieces of exclusive-or gate. Clock ends of D15-D0 of D trigger are connected to same clock signal. Setting ends of D15-D9 and D2 as well as zero setting ends of D8-D3 and D1, D0 are connected to frame synchronizing pulse. Thus, at time of staring frame, D15-D0 of the feedback shift register is reset to 1111111000000100. After bit-oriented exclusive-or between parallel scrambler and input signal, scrambled signal output is formed. After bit-oriented exclusive-or between de-scrambler and signal, de-scramble is realized so as to form signal output. Features are: simple structure, small power consumption, and high reliability.

Description

technical field [0001] The present invention relates to a coding and decoding circuit of a transmission system, to be precise, relates to a frame synchronous parallel scrambler and a parallel descrambler for a Synchronous Digital Hierarchy (SDH) transmission system, which belongs to the coding control of transmission digital information Circuit technology field. Background technique [0002] Synchronous Digital Hierarchy (SDH, Synchronous Digital Hierarchy) is a digital communication system in an optical fiber communication system, and it is also a set of new international communication standards. The basis of the SDH concept is the Synchronous Optical Network (SONET) proposed by the Bell Institute of Communication Technology in the United States. The Consultative Committee for International Telephony and Telegraphy (CCITT, now ITU-T) accepted the SONET concept in 1988 and renamed it SDH, making it suitable for both optical fiber and microwave and satellite transmission. G...

AI Technical Summary

Problems solved by technology

[0013] Because the circuit structure of the parallel scrambling code is more complex, it takes up more resources when it is implemented with a field programmable gate array (FPGA) device, and it takes

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