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Production process of high-quality plumbous zirconate titanate film for ferroelectric memory intergrated circuit

A technology of integrated circuit and manufacturing process, applied in the field of ferroelectric memory integrated circuit processing

Inactive Publication Date: 2002-09-25
FUJITSU LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0017] Although the process of the '443 patent can produce improved PZT films over the prior art, there is room for improvement in terms of PZT quality and process complexity

Method used

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  • Production process of high-quality plumbous zirconate titanate film for ferroelectric memory intergrated circuit
  • Production process of high-quality plumbous zirconate titanate film for ferroelectric memory intergrated circuit
  • Production process of high-quality plumbous zirconate titanate film for ferroelectric memory intergrated circuit

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Experimental program
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Embodiment Construction

[0038] Specific ways to implement the invention

[0039] Reference figure 1 with 2 The ferroelectric capacitor is generally grown on the thermal oxide layer 100 of the partially completed CMOS integrated circuit wafer. A titanium layer is sputtered on the oxide layer (step 200), and the thickness of the titanium layer is 50-200 Ȧ, preferably 200 Ȧ. This titanium layer is oxidized in an oxygen atmosphere at 300-700°C, preferably at 700°C, for 10 minutes to one hour to form an adhesion layer 102 of titanium dioxide, which enhances adhesion and thus prevents subsequent layers Fall off.

[0040] Sputtering (step 202) the platinum bottom electrode layer 104 on the oxidized titanium adhesion layer 100 has a thickness of 500-2500 Ȧ. In order to obtain the best electrode quality, it is preferably 1000 Ȧ thick. In order to obtain the best electrode quality and the best quality of the PZT layer described below, this layer is deposited by DC sputtering when the substrate temperature is 450-...

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Abstract

A process for the manufacture of a ferroelectric capacitor element for an integrated circuit comprising the steps of: depositing a conductive bottom electrode layer, preferably made of a noble metal; covering the bottom electrode layer with a layer of ferroelectric dielectric material; A first anneal is performed on the ferroelectric dielectric prior to the second electrode layer comprising a noble metal oxide; after deposition of the conductive top electrode layer, an anneal is performed on the ferroelectric dielectric material layer and a second anneal is performed on the top electrode layer . The first and second anneals are rapid thermal anneals.

Description

Technical field [0001] The invention relates to the field of ferroelectric memory integrated circuit processing. In particular, the present invention relates to the deposition and annealing steps for forming the dielectric layer and electrode layer of a ferroelectric capacitor in a ferroelectric memory integrated circuit. Background technique [0002] Standard dynamic random access memory (DRAM) and static random access memory (SRAM) devices are considered volatile memory because the data stored in them is lost when the power is turned off. Persistent memories are those memories that can save data even after a power failure. [0003] At present, there is a great market demand for EEPROM (programmable read-only memory that can be electrically deleted) and flash EEPROM permanent memory. These devices tend to have slow write speeds, with write times often on the order of milliseconds, but read times generally range between 1 nanosecond and 1 microsecond. The huge difference in read ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L27/105H01L21/02H01L21/314H01L21/316H01L21/8246
CPCH01L21/02197H01L21/02266H01L28/56Y10S438/957H01L27/105H01L21/31691
Inventor 格伦·福克斯储钒布莱恩·伊斯泰普高松知广堀井义正中村亘
Owner FUJITSU LTD