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Semiconductor memory device and method for selecting multi-word-line in said device

A storage device, semiconductor technology, applied in the direction of static memory, digital memory information, information storage, etc.

Inactive Publication Date: 2002-11-20
FUJITSU SEMICON LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The issue occurs due to multiple modules working with the same timing

Method used

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  • Semiconductor memory device and method for selecting multi-word-line in said device
  • Semiconductor memory device and method for selecting multi-word-line in said device
  • Semiconductor memory device and method for selecting multi-word-line in said device

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no. 1 example

[0078] FIG. 8 is a schematic block diagram of a semiconductor bulk memory device 100 according to a first embodiment of the present invention. The semiconductor memory device 100 includes four memory cell blocks BL0 , BL1 , BL2 , BL3 , a plurality of sense amplifier groups 1 , a plurality of module control circuits 21 , a plurality of sense amplifier driving circuits 22 and a plurality of row decoders 23 .

[0079] Each block BL0-BL3 is connected to an associated sense amplifier bank 1 and row decoder 23 .

[0080] Each row decoder 23 selects a word line in an associated one of blocks BL0-BL3. Each sense amplifier group 1 has a plurality of sense amplifiers 8 . Each sense amplifier 8 amplifies the sensed cell information when a word line is selected. Each module control circuit 21 has a multi-word line selection function that simultaneously selects a plurality of word lines in a plurality of modules.

[0081] Each sense amplifier driving circuit 22 controls the activation a...

no. 2 example

[0120] Figure 12 and 13 Operation timing of the semiconductor memory device 200 according to the second embodiment of the present invention is shown. The circuit structure of the semiconductor memory device 200 of the second embodiment is the same as that of the memory device 100 of the first embodiment.

[0121] The input timing of the block address signal Bad is changed in the semiconductor memory device 200 to simultaneously select word lines in a plurality of blocks other than the first selected word line.

[0122] now refer to Figure 12 Operations of the module control circuit 21, the sense amplifier drive circuit 22, and the row decoder 23 are described.

[0123] In the block BL0 , when the block control circuit 21 is supplied with the block address signal Bad, the block set timing signal Bstt is supplied to the block control circuit 21 . As a result, the block selection signal Bsl becomes high level, and the word line reset signal WLrs becomes low level.

[0124]...

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Abstract

A semiconductor memory device which reduces the time required for performing a multi-word line selection test and operates stably. The semiconductor memory device includes a memory cell module, a row decoder, a sense amplifier, a module control circuit, and a sense amplifier drive circuit. Each module control circuit generates a reset signal. The reset signal is used to select word lines with the row decoder at different timings according to module execution. Each module control circuit provides a reset signal to an associated row decoder. The module control circuit also provides a reset signal to the relevant sense amplifier driving circuit, so that the sense amplifier is released according to different timings between modules.

Description

Background technique [0001] The present invention relates to semiconductor memory devices, and more particularly, to a method for testing interference between adjacent cells that shortens time and avoids noise. [0002] Adjacent cell disturbance testing is performed on semiconductor devices, especially for DRAM devices. During the adjacent cell disturbance test, a specific line remains selected for a predetermined time, and the amplifier is urged to amplify the cell information read from the bit line. Then, disturbance is detected from cell information stored in memory cells connected to adjacent word lines. [0003] As the storage capacity of semiconductor memory devices increases, the number of word lines increases. The time required to perform neighbor cell interference detection is extended. In order to save the test cost, it is necessary to reduce the test time. Therefore, a selection test of a plurality of word lines is performed to simultaneously activate the plural...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/28G11C29/00G11C29/34
CPCG11C29/34G11C29/00
Inventor 中川祐之
Owner FUJITSU SEMICON LTD