Method for minimizing short channel effect of semiconductor devices and transistors

Abstract

A semiconductor device includes at least two transistors, one conduct layer, one grid oxide layer and one grid electrode structure. Each transistor includes the source electrode region, the drain electrode region and the shallow grooves structure formed between the source electrode region and the drain electrode region. The shallow groove structure adjacent to the source electrode region and the drain electrode region insulates them, making short channel effect of transistors be minimized. The conduct layer allocated on the source electrode region, the shallow groove structure and the drain electrode region is connected to the source electrode region and the drain electrode region electrically to be as the channel region. The grid electrode is formed on the grid oxide layer allocated on the conduct layer.

Description

technical field [0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor structure that minimizes or eliminates short-channel effects and reduces bit line resistance. Background technique [0002] The device characteristics of traditional metal-oxide-siliconfield-effct transistors (hereinafter referred to as MOSFETs) such as the threshold voltage (threshold voltage) and the sub-startup current (subthreshold current) can generally be determined by mathematics formula to predict. However, the current trend in integrated circuit manufacturing is to produce MOSFETs with reduced feature sizes, such as channel length dimensions. When the channel length is reduced to the same width as the source and drain depletion regions of MOSFETs, some of the charge in the channel region will combine with the charge in the source and / or drain depletion regions, causing a portion of the channel region to become Depletion, which makes the MOSFETs'...

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However, this approach results in an increase in bit line impedance

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