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Semiconductor memory delay circuit

一种延迟电路、延迟链的技术，应用在静态存储器、数字存储器信息、信息存储等方向，能够解决存储器器件故障、ATD电路输出信号波动等问题

Inactive Publication Date: 2012-05-23
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] As the power supply voltage changes, the output signal fluctuation of the ATD circuit may lead to failure of the memory device

Method used

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  • Semiconductor memory delay circuit
  • Semiconductor memory delay circuit
  • Semiconductor memory delay circuit

Examples

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Embodiment Construction

[0024] It should be understood that the following description of exemplary embodiments is illustrative only and should not be considered as limiting the present invention.

[0025] In the following detailed description, specific details are set forth in order to provide a thorough understanding of exemplary embodiments of the invention. It will be apparent, however, to one skilled in the art that the exemplary embodiments of the invention may be practiced without these specific details.

[0026] Figure 4 is a circuit diagram of a delay circuit of an exemplary embodiment of the present invention. Such as Figure 4 The delay circuit shown can be used in general flash memory. For example, the delay circuit of the exemplary embodiment of the present invention can be used with as figure 1 The general flash memory shown is used in combination. However, these exemplary embodiments may be used in other circuit arrangements according to design requirements.

[0027] refer to F...

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Abstract

A circuit includes an input for receiving an input signal, a delay chain connected to the input for delaying the input signal, and a circuit configuration connected to the delay chain downstream of the input, the circuit configuration for supplying a voltage to the delay chain in response to the input signal.

Description

[0001] This U.S. nonprovisional patent application claims priority to Korean Patent Application No. 2002-19951 filed April 12, 2002 pursuant to 35 U.S.C. §119, which is hereby incorporated by reference in its entirety. technical field [0002] The present invention relates generally to semiconductor memories, and more particularly to semiconductor memories employing delay circuits. Background technique [0003] A semiconductor memory can control its internal circuits by signals having various operation timings. To establish the timing of the various signal operations, delay circuits may be employed along the signal propagation path. In particular, high-frequency memories such as DRAM, SRAM and flash memory can utilize address transition detection (Address Transition Detection, ATD) circuits to respond to address transitions to access memory core circuits such as sense amplifiers and memory cells. [0004] figure 1 A conventional general flash memory is shown. A general fl...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C11/34G11C11/4076G11C8/00G11C8/18H03K5/08H03K5/13H03K5/1534
CPCH03K5/1534H03K5/082G11C8/18G11C8/00
Inventor 赵志虎李升根
Owner SAMSUNG ELECTRONICS CO LTD