Structure of non-volatility memory and its operation method

Abstract

The present invention relates to a non-volatile memory structure and its operation method. The structure of non-volatile memory is formed from several memory locations, several character lines, several drain lines and several source lines. The several memory locations are formed into several memory location groups by using every two memory locations as one group, these memory location groups are parallelly-arranged into a row-column array, all the memory locations in all the memory location groups in every row share a source zone, and adjacent two memory location groups in every row share a drain zone, and the source zone of every memory location of every memory location group in every row is respectively coupled to its correspondent source line, and the drain zone is respectively coupledto its correspondent drain line.

Description

technical field [0001] The present invention relates to the structure and operation method of a non-volatile memory (Non-Volatile Memory), and in particular to an electrically erasable and programmable The structure and operation method of Electrically Erasable Programmable Read Only Memory (EEPROM). Background technique [0002] The electrically erasable and programmable read-only memory in the non-volatile memory has the advantage of being able to store, read, and erase data multiple times, and the stored data will not disappear after power off. Therefore, it has become a memory element widely used in personal computers and electronic equipment. [0003] A typical electrically erasable and programmable read-only memory uses doped polysilicon to make a floating gate (Floating Gate) and a control gate (Control Gate). When the memory is programmed, the electrons injected into the floating gate are uniformly distributed throughout the polysilicon floating gate layer. Howeve...

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Problems solved by technology

Thus making the programming steps more troublesome

[0009] On the other hand, the above-mentioned known silicon nitride read-only memory array uses buried source lines and buried bit lines, so its resistance is high, and the operation speed of the memory cells cannot be improved.

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