Method for designing semiconductor device

Abstract

In a mixed-loaded type semiconductor device including a plurality of MOS transistors having gate insulating films different in thickness, the antenna standard for the MOS transistor having the gate insulating film with a thickness equal to or smaller than a predetermined thickness is relaxed compared with that for the MOS transistor having the gate insulating film with a thickness larger than the predetermined thickness. In particular, the antenna standard for the MOS transistor having the gate insulating film with a thickness equal to or smaller than 2.6 nm allowing the tunneling of the electric charges to occur is relaxed compared with that for the MOS transistor having the gate insulating film with a thickness larger than 2.6 nm.

Description

technical field [0001] The present invention relates to a method of designing a semiconductor device including semiconductor elements each having a gate insulating film. In particular, the present invention relates to a method of designing a semiconductor device in which a plurality of semiconductor elements having different gate insulating films are formed integrally with each other on the same substrate. Background technique [0002] In semiconductor elements each having a gate insulating film, such as MOS transistors, problems arise due to degradation of reliability of the gate insulating film, degradation of characteristics of the gate insulating film, or breakdown of the gate insulating film during the manufacture of these elements. For example, in a semiconductor device including a MOS transistor as a semiconductor element, a gate insulating film made of a silicon oxide film or the like is formed on a semiconductor substrate while polysilicon, aluminum or the like Aft...

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Problems solved by technology

However, this leads to limitations in the design of via holes and upper layer wiring in one semiconductor device

Therefore, there arises a problem that the degree of freedom of design is reduced

In particular, in recent years, if the improvement of high integration, high performance, and low-voltage operation of semiconductor devices is adopted to reduce wiring width, increase wiring density, improve multilayer wiring, and increase the area of ​​semiconductor devices, the total wiring length will increase. , and the number of vias connected to the routing will increase

This results in an increase in the antenna electrode area

On the other hand, since the antenna ratio can easily be significantly increased due to reduction in gate electrode area or due to scaling down of MOS transistors, the degree of freedom in design is increasingly reduced

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