Data processing system capable of using virtual memory processing mode

Abstract

An aliasing support for a data processing system having no system memory is disclosed. The data processing system includes multiple processing units. The processing units have volatile cache memories operating in a virtual address space that is greater than a real address space. The processing units and the respective volatile memories are coupled to a storage controller operating in a physical address space. The processing units and the storage controller are coupled to a hard disk via an interconnect. The processing units contains an aliasing table for associating at least two virtual addresses to a physical disk address directed to a storage location in the hard disk. The hard disk contains a virtual-to-physical translation table for translating a virtual address from one of said volatile cache memories to a physical disk address directed to a storage location in the hard disk without transitioning through a real address. The storage controller, which is coupled to a physical memory cache, allows the mapping of a virtual address from one of the volatile cache memories to a physical disk address directed to a storage location within the hard disk without transitioning through a real address. The physical memory cache contains a subset of information within the hard disk.

Description

technical field [0001] The present invention relates generally to data processing systems, and more particularly to data processing systems having memory hierarchies. More specifically, the present invention relates to data processing systems capable of managing virtual memory processing modes without the assistance of an operating system. Background technique [0002] Existing memory hierarchies typically include one or more levels of cache memory, system memory (also known as real memory), and hard disks (also known as physical memory) connected to processor components via input / output channel switches. When there are multiple levels of cache memory, the first level cache, commonly referred to as the level one (L1) cache, has the fastest access time and the highest cost per bit. Other levels of cache memory, such as level two (L2) cache and level three (L3) cache, have slower access times and a relatively lower cost per bit. Generally, the lower the cache memory level, t...

AI Technical Summary

Problems solved by technology

However, there are many problems with using the operating system to manage virtual memory

For example, the VMM usually has no knowledge of the hardware structure, so a VMM-controlled replacement policy is usually not very effective

In addition, VMM code is very complex, and maintaining VMM code across multiple hardware platforms or a single hardware platform with many different memory configurations is very complex and expensive

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