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Multi channel digital signal generator

A digital signal and generator technology, applied in the field of digital communication, can solve the problems of difficult system integration, low timing accuracy, and inability to generate many channel waveforms.

Inactive Publication Date: 2004-06-30
NO 30 INST OF CHINA ELECTRONIC TECH GRP CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0002] At present, the existing single-chip microcomputer realizes the square wave scheme of arbitrary duty ratio, which is to control the IO pin to output I and O regularly through the single-chip software software, so as to achieve the purpose of outputting a square wave with any duty ratio from one to multiple channels. The main application fields of this technical scheme It is used as an independent signal generator; the main disadvantages of this technical solution are: it is not designed for embedded applications, the system integration is difficult, the timing accuracy is not high, and it is limited by the instruction cycle of the single-chip microcomputer, so it cannot generate high-frequency waveforms, such as 100MHz; at the same time Limited by the number of microcontroller pins, it is impossible to generate waveforms with a large number of channels

Method used

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Embodiment 1

[0029] as attached figure 1 and 2 . The present invention includes analyzing the signal module to be generated, selecting the system clock module, determining the state number module, generating the excitation source module, filling in the output signal module, drawing the state transition diagram module, translating into a hardware code module, compiling and debugging module, characterized in that: : The finite state machine completes each state transition sequentially under the drive of parameters determined by analyzing the signal module to be generated, selecting the system clock module and determining the number of states, and then outputs the specified number and Specify the length and relative position of the digital signal, and assign values ​​to each state output signal by filling in the output signal module according to the high and low levels of the corresponding time period of the output signal, and then draw the state transition diagram module to facilitate readi...

Embodiment 2

[0036] Such as Figure 4 . The selection system clock module of the present invention is the core of the finite state machine, which drives the automatic operation of the finite state machine, and its clock frequency determines the frequency and precision of the output waveform.

[0037] The longest clock period in the present invention cannot exceed the frequency of the output signal.

[0038] When the selection system clock module of the present invention generates corresponding two output signals, the clock period is minutes.

[0039] in the attached Figure 4 Among them, two output signals are generated, and their clock periods are 10ns and 20ns.

Embodiment 3

[0041] produced as Figure 6 The output of periodic signals W1 and W2 shown has a signal resolution of 10ns, that is, 100MHz, so a 100MHz clock should be selected, and the minimum co-multiple cycle of W1 and W2 is 30ns, so the number of selected states is 3. Since it is a self-excited periodic signal, no excitation signal is used. combined with Figure 5 , the upper part shows an input signal CLK, two input signals W1 and W2, S1, S2, and S3 are the three states of the finite state machine, and the arrow indicates the direction of conversion. Figure 5 The box on the right of , indicates the output signal status in various states.

[0042] It is implemented in VHDL or Verilog language, with strong readability and portability.

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Abstract

The generator comprises module for analyzing signal to be generated, module for selecting system clock, module for determining status number, and module for generating excitation source. With external condition being met, under driving of time clock, finite state machine completes state transition in sequence as well as outputs digital signal waveform in designated number. When external excitation condition is met, finite state machine enters a state in every other clock cycle time. Under different states, finite state machine outputs different signal levels. The invention provides a method of generating digital signal with multiple channels and arbitrary duty ratio for personnel of programming hardware. The functional modules can be integrated into users' programmable hardware design simply and seamlessly.

Description

Technical field: [0001] The invention relates to the technical field of digital communication, in particular to a generator for generating multi-channel digital signals with arbitrary duty ratios. Background technique: [0002] At present, the existing single-chip microcomputer realizes the square wave scheme of arbitrary duty ratio, which is to control the IO pin to output I and O regularly through the single-chip software software, so as to achieve the purpose of outputting a square wave with any duty ratio from one to multiple channels. The main application fields of this technical scheme It is used as an independent signal generator; the main disadvantages of this technical solution are: it is not designed for embedded applications, the system integration is difficult, the timing accuracy is not high, and it is limited by the instruction cycle of the single-chip microcomputer, so it cannot generate high-frequency waveforms, such as 100MHz; at the same time Limited by the...

Claims

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Application Information

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IPC IPC(8): H04L7/02H04L69/40
Inventor 冷冰
Owner NO 30 INST OF CHINA ELECTRONIC TECH GRP CORP
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