3 results about "Clock cycle time" patented technology

The invention discloses a half-cycle time sequence repairing method and system of a circuit delay locked storage device. The method comprises the following steps: detecting whether installation time violation or holding time violation exists in the digital circuit design or not; when the time sequence violation exists and cannot be conventionally repaired, verifying whether the time sequence margin of the violation path meets a calling condition or not; if yes, part of clock cycle time is called through the barrier-free passing characteristic of the circuit delay lock storage device in the high-level stationary circuit period, and half-cycle cycle time calling repair based on the circuit delay lock storage device is carried out on a violation path, specifically, for installation time violation, an end device is replaced; for holding time violation, a reverse trigger device is inserted. Through the half-cycle period time calling and differentiation strategy, the technical bottleneck of a traditional method is broken through, and a final solution is provided for time sequence violation which cannot be repaired by a conventional method in an extreme design environment.

This invention belongs to the field of embedded software technology and discloses an MD5 algorithm optimization method and system based on embedded software. In byte data processing, this method uses a defined MD5 calculation main function combined with three interface functions and data structures to form an MD5 calculation module. This module provides MD5 cycle-by-cycle calculation services for byte data processing to the upper-level user module and determines whether each clock cycle times out. This invention proposes an optimization method for the MD5 algorithm in embedded software. Leveraging the consistency of the algorithm's calculation process in each loop, the total time consumed by the algorithm is evenly distributed across several adjacent software cycles, effectively preventing timeouts in individual cycles caused by calling the MD5 algorithm function. Furthermore, this method does not use system calls related to multi-threaded operations, is independent of the operating system platform, and facilitates software code portability and promotion.

A method and system for building a block data transfer (BT) DRAM provides a solution to fix the performance gap between memory and processor. The data conversion time per word between the analog circuits and the digital circuits inside the BT DRAM is smaller than the processor clock cycle time, that enables the average data transfer speed of a BT DRAM to match to the operation speed of a processor. When continuously transferring a plurality of data blocks, a BT DRAM can achieve a close-to-zero-latency performance and is completely self-refreshing.